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danda821
Joined: 18 Jun 2002
Posts: 141
Helped: 2
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 31 Jan 2007 21:10 question about DFF |
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Hi,
Is there any easy way to model DFF with set and reset using normal DFF and logic gates? Thanks.
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shahal
Joined: 11 Jan 2007
Posts: 49
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| 02 Feb 2007 4:14 Re: question about DFF |
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I have forgotten what set does, I think it sets the value of the flop to 1? The following should work.
Reset part should be easy. Attach the Q pin of the flop to the A pin of a two input AND gate. Pin B on the AND gate is your reset. If you attach the output the AND gate to the A pin of a two input OR gate, then the B pin of the OR gate can be your Set pin.
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rangans
Joined: 11 Mar 2006
Posts: 2
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| 03 Feb 2007 21:05 Re: question about DFF |
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What shahal mentions wont work as the effect of set or reset has to stay even after set/ reset is gone till the next data comes in. One way to do this for a synchronous reset/set is to do what shahal mentioned (OR for set and AND for reset) but do it with the D pin (input data) so that when CLK comes in and when SET/RESET is present either a zero or one would get clocked in instead of the actual data. There is no way though to modify it in such way you can set/reset asynchronously. Hope it helps.
-Ranga
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shahal
Joined: 11 Jan 2007
Posts: 49
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| 04 Feb 2007 0:08 Re: question about DFF |
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| I am not sure I understand why this wont work, now that I think of it. If one input of an AND gate is set to zero. the output will always be zero regardless of what comes into the other input from the Q pin of the flop. Similar situation for the OR gatye also if one of the input is set to 1.
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wice
Joined: 30 Dec 2006
Posts: 39
Helped: 4
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| 06 Feb 2007 8:13 question about DFF |
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why not try this ? (provide that set is valid when set=1; reset is valid when reset=1)
make Q=D (/SET) (/RESET)+VCC(SET)(NOT RESET)+GND(/SET)(RESET)
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