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Constraining Multiple clock design
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no_mad



Joined: 10 Dec 2004
Posts: 253
Helped: 20
Location: Naboo
Post15 Jan 2007 7:34   

Constraining Multiple clock design
Hi all,

I'm using Mentor Graphic tools to synthesize my design (Leonardo Spectrum: ASIC and Precision RTL: FPGA).

The problem is I'm not very sure on constraining a multiple clock design. Someone please share with me some TCL scripts (LeoSpec & Precision) on constraining multi-clock design. It will be a good reference for me and to other people.

At least, a guideline on this issue.
Any suggestions and/or advice are most welcome and highly appreciated.

Thanks in advance,
no_mad
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r63511



Joined: 26 Jul 2006
Posts: 27
Post31 Mar 2007 9:15   

Constraining Multiple clock design
a point to start with:
create the clock for each domain, set multi-cycle or false path for cross-domain signals, but you must be very cautious that those false paths won't hide potential violations.
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zyphor



Joined: 22 Nov 2003
Posts: 100
Helped: 1
Post31 Mar 2007 10:29   

Re: Constraining Multiple clock design
pls find this issue in Prime time guide
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