| Author |
Message |
jkchen
Guest
|
 07 Jun 2002 2:50 xilinx timing constrain problem |
|
| tags: attribute uselowskewlines |
|
|
i want to perform a serial-in-parallel-out registor.all bufg resource is run out in my spartanii chip.i try two methods:
1.add attribute "uselowskewlines" to the clock net;
2.constrain the clock net and d-flip-flop delay in 20ns;
but it can not solve the problem.is there any other methods i missed?
|
|
| Back to top |
|
 |
standing_fist
Joined: 21 Feb 2002
Posts: 11
|
| 07 Jun 2002 17:13 switch bufg to secondary global buffers |
|
|
|
|
|
|
| Back to top |
|
|
jkchen
Guest
|
| 09 Jun 2002 6:44 spartanII just got 4 bufg to use. |
|
|
|
|
| I have used all for other clocks. no more left.
|
|
| Back to top |
|
|
buzkiller
Joined: 01 Jan 1970
Posts: 144
|
| 09 Jun 2002 19:10 |
|
|
|
|
Give us some more information.
| Quote: |
| but it can not solve the problem |
. What is the problem ? I hope you didn't used a PERIOD constraint for data.
regards,
Buzkiller.
|
|
| Back to top |
|
|
jkchen
Guest
|
| 10 Jun 2002 15:44 problem solved |
|
|
|
|
reply from xilinx web site.they suggest two methods:
1.use a clock which pass through a bufg(five times than my clock) sample my clock. this methods can make my clock's rising-edge as accuracy as bufg clock.
2.use floorplan to place the nessary logic in a small area.
i used method 1 and plus "uselowskewlines"(i don't know it's useful or not).the problem is solved.
sorry for my poor english.
jkchen
|
|
| Back to top |
|
|
wjhzhx
Joined: 25 Mar 2002
Posts: 22
|
| 17 Jan 2003 8:50 |
|
|
|
|
You test this:
NET xxx MAXSKEW = 0.5 ns;
xxx is your clock which is not drived by bufg.
|
|
| Back to top |
|
|
tianxiaduzun
Joined: 25 Oct 2001
Posts: 18
Location: canada
|
| 17 Jan 2003 18:19 |
|
|
|
|
| you should edit the constraint file, and include the constraint file when you synthesize it
|
|
| Back to top |
|
|
