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shnain
Joined: 07 Jan 2007
Posts: 38
Helped: 2
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 11 Jan 2007 20:41 power vs area in DC |
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Hello everybody,
Clock gating is a trick for reducing power consumption of a circuit, but when activating this feature in DC power compiler, I was surprised that the total gate count of the circuit decreases. It's a good thing, but I want to know why ?
Also, the test coverage decreases due to clock gating logic. Is there any work around to regain observability on these points ?
Thanks & regards,
Said.
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11 Jan 2007 20:41 Ads |
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research235
Joined: 15 Mar 2006
Posts: 293
Helped: 16
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11 Jan 2007 22:33 Re: power vs area in DC |
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Hi
I remember readings some thing abt this in synopsys manual . Please refer the power management manual
suresh
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cheelgo
Joined: 23 Nov 2004
Posts: 84
Helped: 3
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12 Jan 2007 7:05 Re: power vs area in DC |
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| shnain wrote: |
Hello everybody,
Clock gating is a trick for reducing power consumption of a circuit, but when activating this feature in DC power compiler, I was surprised that the total gate count of the circuit decreases. It's a good thing, but I want to know why ?
Also, the test coverage decreases due to clock gating logic. Is there any work around to regain observability on these points ?
Thanks & regards,
Said. |
I am not power compiler project, this will be act as one constraint.
the test coverage decrease due to control of some clock gating cell is not fully enabled during scan capture.
this is not due to the controllability of the design from my point of vew.
regards,
cheelgo
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