SystemC

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SivabalanBalasundram

Joined: 08 Jun 2006
Posts: 6

05 Jan 2007 4:32 multiplexer systemc code

Hello.. I m a VHDL user and a I new to SystemC. I will be using SystemC for my project and I m having some problem understanding how SystemC works. Previously in VHDL we just need to create a single code our simple design like adder, multiplexer and etc .However I am a little confused from the examples I have referred from the web for SystemC. I don’t understand why we need 3 files ( SystemC code, testbench, and simulation file) for a single design to be executed in Visual C++ 6.0 for SystemC.

http://www.cs.ucr.edu/~vahid/sproj/SystemCLab/lab1a.htm

I Understand the System C code because it is similar the the VHDL code however I don’t understand how to generate/create the test bench and the simulation file.!Do we have to create these 2 files (testbench, and simulation file) or is there any way that they can be generated.. Please some one help me!!!

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rakesh_aadhimoolam

Joined: 14 Mar 2006
Posts: 218
Helped: 16

05 Jan 2007 11:09 Re: SystemC

Hi..........

whether it is systemC or VHDL or verilog........you always require a testbench to validate the result.............ok

i think you might have worked in VHDL on modelsim platform wherein you may not require a testbench to be written.....instead you insert the values directly......

But if you go for other tools you definately require a testbench..........

good luck..............