Rules | Recent posts | topic RSS | Search | Register  | Log in

Which kind of PLL jitter affect the timing in STA

 
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Author Message
albred



Joined: 01 Aug 2005
Posts: 49
Location: china
Post25 Dec 2006 7:03   Which kind of PLL jitter affect the timing in STA
Here is the definitions of "PLL period jitter" and "PLL cycle-to-cycle jitter" bellow.
Which jitter should be considered as "clock uncertainty" in STA (just for setup check, no affect to hold check)?

Period Jitter (A), (JEDEC Definition - JESD65)
The edge deviation to the ideal FOUT when measuring the rising edge of FOUT after
(n+N)-th cycle by using the rising edge of FOUT at n-th cycle as the trigger point, where N=1. FOUT is PLL's output.(figure 1)
Cycle-to-Cycle Jitter (JEDEC Definition - JESD65)
The cycle time variation between adjacent cycles over a random sample of adjacent clock cycle pairs.(figure 2)

Sorry, but you need login in to view this attachment
Back to top
Guru59



Joined: 10 Jul 2006
Posts: 232
Helped: 4
Post25 Dec 2006 7:12   Re: Which kind of PLL jitter affect the timing in STA
I think it is PERIOD JITTER which may cause Problems in STA.....

correct me if i'm wrong.....
Back to top
johnma



Joined: 17 Dec 2006
Posts: 17
Post26 Dec 2006 6:43   Which kind of PLL jitter affect the timing in STA
I think you are right. You can use set_clock_uncertainty command to consider colck jitter and skew.
Back to top
xstal



Joined: 12 Oct 2006
Posts: 140
Helped: 19
Location: India
Post26 Dec 2006 13:04   Re: Which kind of PLL jitter affect the timing in STA
Hi guys,
Can you please tell me why and how these jitter occur in the PLL output.
Back to top
albred



Joined: 01 Aug 2005
Posts: 49
Location: china
Post27 Dec 2006 2:50   Re: Which kind of PLL jitter affect the timing in STA
thanks all.
I think you're right.
Back to top
sumit_techkgp



Joined: 01 Apr 2007
Posts: 135
Helped: 3
Post14 Apr 2007 5:09   Which kind of PLL jitter affect the timing in STA
The jitter occurs out of phase noise, which arises because charge pumping problem.
Sumit
Back to top
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Page 1 of 1 All times are GMT + 1 Hour


Abuse
Administrator
Moderators
topic RSS 
sitemap