Why read clk can't read out any data?

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staraimm

Joined: 21 Oct 2006
Posts: 134
Helped: 3

07 Dec 2006 9:22 Why read clk can't read out any data?

hi, anybody, I wrote the verilog code as follows.

module test(inclk, inclr, indata, outclk, outclr, outdata);
input inclk, inclr, outclk, outclr;
input[7:0] indata;
output[7:0] outdata;

reg[7:0] mem[0:31];
reg[4:0] memcnt;

always @ (posedge inclk or negedge inclr)
begin
if(!inclr)
memcnt <= 0;
else
memcnt <= memcnt + 1;
end

always @ (posedge inclk)
begin
mem[memcnt] <= indata;
end

reg[4:0] rdcnt;

always @ (posedge outclk or negedge outclr)
begin
if(!outclr)
rdcnt <= 0;
else
rdcnt <= rdcnt + 1;
end

assign outdata = mem[rdcnt];

endmodule

Assume the inclk is about 15Mhz, and the outclk is about 10Mhz. I compiled the code with the QuartusII web version. But in the first 8 clock, I can't get the correct data on the bus. Can anybody tell me why? Thanks.

staraimm

Joined: 21 Oct 2006
Posts: 134
Helped: 3

08 Dec 2006 1:36 Re: Why read clk can't read out any data?

Can anyboday give me a answer?

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nand_gates

Joined: 19 Jul 2004
Posts: 907
Helped: 120

08 Dec 2006 5:06 Re: Why read clk can't read out any data?

Can you POST ur testbench for the code you have pasted??

staraimm

Joined: 21 Oct 2006
Posts: 134
Helped: 3

08 Dec 2006 7:30 Re: Why read clk can't read out any data?

I compile the code using the qu(at)rtus. And I used the waveform not the testbench.

nand_gates

Joined: 19 Jul 2004
Posts: 907
Helped: 120

08 Dec 2006 9:05 Re: Why read clk can't read out any data?

May be you can post the picture of ur waveforms then!

staraimm

Joined: 21 Oct 2006
Posts: 134
Helped: 3

08 Dec 2006 10:59 Re: Why read clk can't read out any data?

The waveform is attached. I want to know why the value between "02" and "04" is "00"? I think the value should be "03".

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echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

08 Dec 2006 15:04 Re: Why read clk can't read out any data?

I agree with your "03" expectation. I don't see any obvious explanation. Maybe the synthesis didn't happen correctly, or maybe your simulator is broken.

What type FPGA/CPLD is this? Perhaps someone else can try it for you (I don't have Al.tera tools). It works fine in Xilinx. Here is a Spartan-3 post-route simulation.

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