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leeguoxian
Joined: 20 Jun 2006
Posts: 54
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 06 Dec 2006 6:47 why not add buffer but lockup ?? |
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Dear All :
In DFT, it will add lockup latch where there are different clock domain in one scan chain to avoid hold time violation .
But if the skew is greater than half of the cycle , I think lockup latch will not solve the hold time violation .
Why don't we add buffer instead of latch ??
Thanks
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spauls
Joined: 17 Dec 2002
Posts: 547
Helped: 19
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| 07 Dec 2006 10:27 Re: why not add buffer but lockup ?? |
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| Because if you take buffer, you have to use huge buffer and you will end up in EMI problems.
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leeguoxian
Joined: 20 Jun 2006
Posts: 54
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| 10 Dec 2006 13:39 why not add buffer but lockup ?? |
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Dear Spauls :
What's EMI ?
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blacksmith_vlsi
Joined: 29 Nov 2006
Posts: 12
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| 11 Dec 2006 4:21 Re: why not add buffer but lockup ?? |
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EMI is electron-magnetic interference. EMI get more serious with chip process goes down. Antenna rule check is to avoid layers forms a antenna which will cause serious EMI.
Bus as said that huge buffer can cause EMI problem,... actually i don't really know how it does. Maybe someone can help us.
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niranr
Joined: 20 Dec 2006
Posts: 4
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| 20 Dec 2006 9:40 why not add buffer but lockup ?? |
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| buffer doesn't solve problem of skew, whereas lockup latches solves this and infact buffer adds more delay.
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sheikh145
Joined: 10 Jan 2007
Posts: 6
Location: Bangalore
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| 29 Jan 2007 5:21 why not add buffer but lockup ?? |
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| hi all can u let me know more about EMI
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shahal
Joined: 11 Jan 2007
Posts: 49
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| 29 Jan 2007 5:57 Re: why not add buffer but lockup ?? |
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| Dont know much about this, but wont it add an "enabler circuit" (back to back flops) if the frequency difference between the two clock domains is more than two times the frequency of the slower clock?
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sheikh145
Joined: 10 Jan 2007
Posts: 6
Location: Bangalore
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| 06 Feb 2007 13:25 why not add buffer but lockup ?? |
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| well thanks shahal,but i couldn't get much out of it.It will be really useful to me if u cud elaborate more on it.Thanks
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dr_dft
Joined: 10 Aug 2005
Posts: 87
Helped: 1
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| 08 Feb 2007 7:12 why not add buffer but lockup ?? |
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shahal, leeguoxian,
Frequency of operation is not as important during scan shifting. Therefore, we can always slow down the freq and/or modify the duty cycle to remove a hold time problem with data lockup latches.
If your skew is big, then you will need a lot of buffers or delay cells, which is undesirable for power/area etc.
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ericyuan
Joined: 08 Mar 2006
Posts: 37
Helped: 1
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| 08 Feb 2007 11:22 Re: why not add buffer but lockup ?? |
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how to deal with the lockup latch between two clock domain?
just treat it as an endpoint? or transparency ?
Is there anything else should be considered?
it is difficult for STA while eliminate the skew and hold time violation.
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dr_dft
Joined: 10 Aug 2005
Posts: 87
Helped: 1
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| 08 Feb 2007 16:59 why not add buffer but lockup ?? |
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Eric,
If the 2 clock domains are fully controllable from chip pins, you can false path them, and tweak the timing on the ATE.
If the 2 clock domains are muxed into one bypass clock, then create_clock at the common bypass clock in STA with your reduced scan frequency, constrain it to scan mode, and your STA should be able to figure out whether there is a violation or not.
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ericyuan
Joined: 08 Mar 2006
Posts: 37
Helped: 1
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| 09 Feb 2007 5:58 Re: why not add buffer but lockup ?? |
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| dr_dft wrote: |
Eric,
If the 2 clock domains are fully controllable from chip pins, you can false path them, and tweak the timing on the ATE.
If the 2 clock domains are muxed into one bypass clock, then create_clock at the common bypass clock in STA with your reduced scan frequency, constrain it to scan mode, and your STA should be able to figure out whether there is a violation or not. |
i know what you said, so it is safe to check the timing violation while you do not know whether you can tweak it on ATE or not.
STA will treat it as a transparent latch in scan shift/capture mode ,it capture the fastest path and hold it after half cycle(falling edge of a latch)...
pls correct me if i am wrong
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dr_dft
Joined: 10 Aug 2005
Posts: 87
Helped: 1
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| 09 Feb 2007 6:34 why not add buffer but lockup ?? |
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In capture mode, the data lockup latch on the scan chain does not matter, since SE is 0. I hope you are not adding data lockup latches into you normal data path, since this will mess up your functional timing.
In shift mode, assuming you have the following:
FF1->LAT->FF2
STA should check hold from FF1 to latching edge of LAT, and setup from transparent edge of LAT to FF2.
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