SystemVerilog Clocking Block assign data time?

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davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

05 Dec 2006 12:05 SystemVerilog Clocking Block assign data time?

Hi all,

I use Clocking Block to construct testbench component like driver.
And I am confused with what time Clocking Block to synchronize data.

For example, there is "sync_fifo_if_i" interface instance and "wr_driver_cb" clocking block.
The clocking block is

Code:

//-----
clocking wr_driver_cb @ (posedge clk);
default input #setup_time output #hold_time;
input full,almost_full;
output din,wr;
endclocking : wr_driver_cb
//-----

The data assignment sequence is

Code:

//-----
@(sync_fifo_if_i.wr_driver_cb)
din <= data_in;
wr <= 1'b1;
@(sync_fifo_if_i.wr_driver_cb)
//-----

The questions are
1. Will data assignment (synchronize) at the first @... or the second @...theoretically?
2. Is

Code:

@(...) din<=data_in;

and

Code:

@(...); din<=data_in;

(note the ; difference in @) difference?

Thanks!
Best regards,
Davy

spauls

Joined: 17 Dec 2002
Posts: 547
Helped: 19

07 Dec 2006 10:22 Re: SystemVerilog Clocking Block assign data time?

Davvy ,

Both will do same job.

Guru59

Joined: 10 Jul 2006
Posts: 235
Helped: 4

07 Dec 2006 16:19 Re: SystemVerilog Clocking Block assign data time?

Hi......davyzhu

i want to know abt system verilog as well it will be really great if you upload some books related to system verilog................

i have gone through asic-world.com but i want to practice the programming for it..........

thanks...........

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davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

08 Dec 2006 2:07 SystemVerilog Clocking Block assign data time?

Hi Guru59,

There is a SystemVerilog Video Seminar that maybe help.
http://www.demosondemand.com/clients/synopsys/systemverilog/index_new.asp

Thanks!
Davy