Verilog problem: default case to set signal xxxx

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davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

24 Nov 2006 16:48 Verilog problem: default case to set signal xxxx

Hi all,

I always found people like to add default branch like below:

Code:

case(branch)
... ...
[all the possible branch]
... ...
default: signal = 8'bx;

And my friend told me it's for simulation cause. When branch not hit all the possible case, the branch must have something like xxxx. So we set signal to xxxx to let xxxx pass go on and help us to find the bug.

If I set default: signal = 0; the xxxx problem will be hidden and hard to find the bug.

But as we know, there is no xxxx signal in real digital world. So is there any better method to solve the problem?

Best regards,
Davy

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

25 Nov 2006 10:27 Verilog problem: default case to set signal xxxx

No problem, the simulator and synthesizer are both happy with X. During simulation, X means "unknown state", and helps you catch bugs. During synthesis, X means "don't care", and is absorbed during logic optimization. Go ahead and use X, it is very helpful.

In my projects, I set various data buses to X during idle states. ModelSim displays X in red color. That greatly clarifies the data pipelines, helping me to visualize the data flow and catch bugs such as reading data at the wrong time.

darylz

Joined: 24 Mar 2005
Posts: 132
Helped: 4

26 Nov 2006 7:41 Verilog problem: default case to set signal xxxx

it depends on the systhesis tool. in some case, the systhesis tool think "x" as "dont care". x is useful for tracing.

blanket

Joined: 14 Jan 2003
Posts: 30
Helped: 1

26 Nov 2006 17:51 Re: Verilog problem: default case to set signal xxxx

I'm seeking a clarification here!

Is it SOMETIMES or ALWAYS that synthesis tools treat "X" as don't cares?

-B

davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

27 Nov 2006 3:22 Verilog problem: default case to set signal xxxx

Hi echo47,

Nice to meet you again!

You said "In my projects, I set various data buses to X during idle states. ModelSim displays X in red color."

Do you mean just set data buses to X and make control bus dedicated logic 0/1, is it right?

Best regards,
Davy

aslijia

Joined: 03 Nov 2006
Posts: 51
Helped: 1

27 Nov 2006 3:45 Verilog problem: default case to set signal xxxx

in fact, you can't hit all the possible. for instance, 2-bit case varible, you may think 00 01 10 11 is all the possible. but have you thought about 2'bZ0 or 2'b1Z.

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echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

27 Nov 2006 4:30 Re: Verilog problem: default case to set signal xxxx

Hi davyzhu. Yes, my control signals are always 0 or 1 and never X. Similar to reading and writing an ordinary SRAM, the address and data buses are sometimes "don't care", but the read and write enables must always be valid.