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aifi
Joined: 02 Mar 2006 Posts: 35
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14 Nov 2006 8:24 difference design compiler primetime |
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hi all...
why we need DC if we can only use PT for synthesis?
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research235
Joined: 15 Mar 2006 Posts: 293 Helped: 16
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14 Nov 2006 11:33 what is primetime used for |
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hello aify
Using DC r PT depends on wat exatly u will be working on .... for STA PT is best .
suresh
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sree205
Joined: 13 Mar 2006 Posts: 421 Helped: 30
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14 Nov 2006 11:38 design compiler vs primetime |
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Hi,
DC has a timing analysis engine and generates reports on setup, hold violations and slack analysis, but its not as accurate as PT. as far as synthesis goes, according to my knowledge, PT can't synthesize.
Last edited by sree205 on 14 Nov 2006 12:23; edited 1 time in total |
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rsrinivas
Joined: 10 Oct 2006 Posts: 419 Helped: 36 Location: bengalooru
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14 Nov 2006 11:42 primetime timing between cdc |
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I had heard tat PT is for timing verification and DC for synthesis.
formality for formal verification
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research235
Joined: 15 Mar 2006 Posts: 293 Helped: 16
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14 Nov 2006 11:58 difference timing dc prime time |
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hello every one
well according to me .. DC is the only one which can perform the syntheis. and PT can only do timing analysis ..
please let me know if I am wrong
suresh
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rsrinivas
Joined: 10 Oct 2006 Posts: 419 Helped: 36 Location: bengalooru
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14 Nov 2006 14:21 why primetime |
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yes only DC from those mentioned by aifi
other tools like leonardo spectrum is also popular
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research235
Joined: 15 Mar 2006 Posts: 293 Helped: 16
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14 Nov 2006 14:55 timing engine, dc pt |
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ohh yeah ,,
This leonardo spectrum .. is it widely used .. ?
suresh
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mingcol
Joined: 18 Aug 2006 Posts: 11 Helped: 1
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14 Nov 2006 15:14 timing differences between pt and dc reports |
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DC is for synthesis, and can do some simple timing analysis.
but only PT can be a final sign-off STA tool.
PS. they have different algorithm for STA inside themselve.
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asic_bh
Joined: 26 Jul 2006 Posts: 8
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14 Nov 2006 15:23 synopsys design compiler complete timing analysis |
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| DC is synthesis and can do timing analysis also, PT cannot synthesis but PT is good for timing analysis. and PT should be used for STA sign off
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sarath51
Joined: 11 Dec 2002 Posts: 143 Helped: 7
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14 Nov 2006 15:23 what is bc_wc |
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| DC is indusrtey standard tool for synthesis and PT is for Signoff
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rameshsuthapalli
Joined: 27 Jun 2006 Posts: 163 Helped: 19 Location: bangalore,india
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15 Nov 2006 9:28 primetime design compiler 차이 |
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Hi all,
the DC contains the algorthems used in primetime but those r not much accurate as primetime.the DC is mainly ment for the timing optimisation ratherthan timing calculation.
regards,
rameshs
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rsrinivas
Joined: 10 Oct 2006 Posts: 419 Helped: 36 Location: bengalooru
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15 Nov 2006 11:42 primetime ocv |
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hi
the DC contains the algorthems used in primetime but those r not much accurate as primetime.the DC is mainly ment for the timing optimisation ratherthan timing calculation.
regards,
rameshs
Right.
DC and primetime are both from synopsys and it
contains the libraries of PT to support it. leonardo
spectrum is widely used but is not as popular as
synopsys DC.By the way the only tool synopsys
got recognition in the industry was from DC.
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gong.kidd
Joined: 24 Oct 2006 Posts: 19 Helped: 2
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15 Nov 2006 12:11 prime time and dc difference |
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| DC is a widely used synthesis tool for ASIC, and it can do some simple timing analysis; PT is a very effective STA tool.
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zhangpengyu
Joined: 28 Jun 2004 Posts: 177 Helped: 2
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16 Nov 2006 8:45 static timing analysis bc_wc |
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| PT is to do STA,not for synthesis
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maks10
Joined: 09 Jun 2005 Posts: 49 Helped: 3 Location: Bangalore, India
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16 Nov 2006 9:22 dc prime time |
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synopsys, Cadence , Magma & Mentor Graphics are some leading EDA tool companies .First of all thers' no single tool which does the whole flow except in the case of Magma. Each of these companies excel only in a particular area in Design flow. In analog side Cadence is the leader in the whole flow. While in digital side its a combination of all these companies.For doing synthesis synopsys has Design Compiler (commonly called DC). Mentor Graphics synthesis tool is Leonardo spectrum. Cadence synythesis tool is called Build Gates. Magma's well known for their physical design tool. In a synthesis tool there is an internal timing analysis engine which checks whether timing parameters are met or not. But It s not tht accurate. Hence for doing timing analysis a seperate tool is used.
Prime time from synopsys is the industry standard tool for doing it.
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bharat_in
Joined: 05 Oct 2006 Posts: 78 Helped: 2
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16 Nov 2006 10:04 algorithm used in primetime |
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| what does STA stand for?
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aifi
Joined: 02 Mar 2006 Posts: 35
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16 Nov 2006 10:41 synopsys dc vs pt |
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| STA stand for static timing analysis
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copper230230
Joined: 06 Feb 2006 Posts: 8
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17 Nov 2006 5:40 synopsys design compiler leonardo |
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Dear sirs,
But I still don't know exactly the difference between DC & PT.
The PT STA is more accurate than DC. Can take a example?
From the PT refference maual, I know the PT is powerful than DC.
For example, PT can do chip variation analysis. DC seem not.
If I only use the basic function to do STA, for example only
setup/hold time check. Do they still have great difference??
Thanks for your anaswer!!
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shiv_emf
Joined: 31 Aug 2005 Posts: 641 Helped: 16
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21 Apr 2007 15:08 DC vs PrimeTime |
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nice discussion on DC and PT
I am interested to knw algorithms !! what are the algorithms used in PT for STA ?
thanks
Shiv
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energeticdin
Joined: 31 Jul 2006 Posts: 126 Helped: 4
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22 May 2007 13:02 Re: DC vs PrimeTime |
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DC is only for synthesis
PT is for STA(Static Timing analysis)
In PT we will get the input as Synthesis netlist, libraries, Parasitic data information, and SDF
Dinesh
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shiv_emf
Joined: 31 Aug 2005 Posts: 641 Helped: 16
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22 May 2007 15:57 DC vs PrimeTime |
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its nt possible to do synthesis in PT...
thats true...
shiv
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Google AdSense

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22 May 2007 15:57 Ads |
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dozy_walia
Joined: 10 Jan 2007 Posts: 147 Helped: 1
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23 May 2007 19:08 DC vs PrimeTime |
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| what is PT?
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nandhika
Joined: 17 Apr 2007 Posts: 43 Helped: 2
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24 May 2007 6:42 DC vs PrimeTime |
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hi dozy,
PT means Prime Time.......
as all are discussing its used for Timing analysis
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Kul_priya
Joined: 29 Dec 2008 Posts: 1
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29 Dec 2008 11:41 Re: DC vs PrimeTime |
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I am very new to STA & PT. I just started with PT, i am using the same constraints as given to DC. I am getting violations in PT and no violations in DC.
I did a small study and found that the violations in PT are because, we are giving min & max latencies for the clocks while we do create_clock. DC is taking same latency for both Launch & Capture paths but PT is taking the max value for the Launch path and min value for the Capture path (which is the worst case and PT is doing the right thing i guess). This PT run is just after synthesis even before CTS is done, so what is the significance of this min & max latencies? We have given max latency as 1.20ns & min as 40% of it i.e. 0.48ns which is making a difference of 520ns?
Also in PT if the analysis type is set as bc_wc or single, PT also considers same clock latency for both Launch & Capture, but for OCV it takes min 7 max values as said above. So do i need to fix the violations? are they real?
Sorry for the long mail
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santhosh007
Joined: 27 Aug 2008 Posts: 122 Helped: 26 Location: Bangalore
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31 Dec 2008 6:26 Re: DC vs PrimeTime |
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| Kul_priya wrote: |
I am very new to STA & PT. I just started with PT, i am using the same constraints as given to DC. I am getting violations in PT and no violations in DC.
I did a small study and found that the violations in PT are because, we are giving min & max latencies for the clocks while we do create_clock. DC is taking same latency for both Launch & Capture paths but PT is taking the max value for the Launch path and min value for the Capture path (which is the worst case and PT is doing the right thing i guess). This PT run is just after synthesis even before CTS is done, so what is the significance of this min & max latencies? We have given max latency as 1.20ns & min as 40% of it i.e. 0.48ns which is making a difference of 520ns?
Also in PT if the analysis type is set as bc_wc or single, PT also considers same clock latency for both Launch & Capture, but for OCV it takes min 7 max values as said above. So do i need to fix the violations? are they real?
Sorry for the long mail  |
DC is a synthesis tool for asic where as leonardo spectrum should be a synthesis tool for the FPGA designs.
all the synthesis tools(DC,Cadence RC, Magma) can do the timing analysis to the some extent. Basically the synthesis tools try to optimize design based on the timing/power/area constraints supplied by the user. So this timing is some what ok.
PT is purely a timing analysis tool, we do the timing analysis after the place and route so you will have complete parasitica info and the wire length, so you will have complete timing info . STA is a path based timing analysis.
We need to analysis the each path in the design into different mode like functional, test mode and so on, iof any violations you need to fix the either by upsizing the cell or polacing the buffer to meet the timing. if you the violation is too large then you need to go back to place and route or even synthesis level adjust the constraints.
OCV will provide the extra timing margins even the synthesis tools can also support the OCV measures to some extent.
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ljxpjpjljx
Joined: 05 May 2008 Posts: 533 Helped: 12 Location: Shang Hai
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31 Dec 2008 7:12 Re: DC vs PrimeTime |
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| for the timing analysis , the PT is more powerful! the DC is for the synthesis and make a preview of the timing!
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hareeshravi
Joined: 06 Sep 2007 Posts: 3
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03 Jul 2009 10:39 Re: DC vs PrimeTime |
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Hi,
Being a synthesis tool, the main aim of DC is synthesis. It does require some information on timing, but it is not always required. Also custom designed moduled are implemented as such and DC cannot handle post-layout timing analysis.
PT is a good tool in the sence it has a lot of options for Timing analysis. False-paths, CDC, timing with clock phase differences, delay annotated designs e.t.c. can be handled by PT effectievely. Hence it can be used even after Place and Route. That is the reason why PT is preffered for timing analysis..
Regards,
Hareesh
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