electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

how to use sdf file in NC-verilog?
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> how to use sdf file in NC-verilog?
Author Message
peen1



Joined: 02 Nov 2004
Posts: 43
Post13 Nov 2006 0:41   

ncverilog sdf
I have these followng files

test.sdf
a.v,
testbench.v

The testbench.v file instantiates a and test. Everything compile in Nc-launch/verilog and I also get test.sdf.X file but during ncelab it says can't find design test. Also it does not produce a snapshot for simulation.

I have saved test.v in a seperate location and do not compile that.

Does anyone know how to use sdf files in nc-verilog simulation?

Thanks
Back to top
Shurik



Joined: 15 Jul 2004
Posts: 162
Helped: 12
Post13 Nov 2006 17:49   

ncvlog: +sdf
SDF attached in the test bench

initial $sdf_annotate ("test.sdf",<instance of a module>);
Back to top
Google
AdSense
Google Adsense
Post13 Nov 2006 17:49   

Ads


Back to top
vinodkumar



Joined: 05 Oct 2006
Posts: 240
Helped: 10
Post16 Nov 2006 16:14   

nc verilog sdf
hi
u try with this.

in the initial block of test bench write this

initial
begin
$sdf_annotate("/path of sdf.x file",u0);
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> how to use sdf file in NC-verilog?
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
How can i annotate SDF file as Using NC-verilog? (1)
Verilog netlist backannotation from.sdf file, with ModelSim (3)
how to load a sdf file in modelsim 5.7g (3)
how to use sdf extracted from astro ? (3)
how to write sdf file for this and gate ? (1)
PT write SDF file, same Spef file , different uncertaince (3)
SDF file translate to constraint file under Astro (1)
how to use PCAD pcb file as library file (3)
How To Convert VERILOG FILE TO VHDL FILE (2)
SDF file and slk file (7)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS