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whatever
Joined: 02 May 2002
Posts: 18
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 12 May 2002 7:46 Methodology: from fpga to asic? |
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How to convert the fpga to asic quickly, smoothly, and efficiently?
Thx in advance.
Last edited by whatever on 14 May 2002 15:25; edited 1 time in total |
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jetmarc
Joined: 17 Dec 2001
Posts: 54
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| 12 May 2002 14:27 Re: Methodology: from fpga to asic? |
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| whatever wrote: |
How to convert the fpga to asic quickly, smoothly, and efficiently?
Thx in advance. |
ACTEL offers an upgrade path for its FPGA series. They may not be as cost-effective as a "normal" ASIC, but the migration is easy and fast.
jetmarc
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wjhzhx
Joined: 25 Mar 2002
Posts: 22
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| 17 Jan 2003 9:00 |
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| @ltera and Xilinx have the same upgrade path as jetmarc said
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linuxluo
Joined: 26 Jul 2002
Posts: 511
Helped: 4
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| 17 Jan 2003 11:42 |
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Hi,
You can provide your program file to your fpga vendor, and he will do the rest things. And the ASIC from the fpga has the same performace as FPGA you designed.
If you want a true asic , you have to choose a foundry and have other valuable tools and lots of time to do it.
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cbh1024
Joined: 31 May 2001
Posts: 8
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| 17 Jan 2003 11:47 Converting from FPGA to ASIC |
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Try to write clean synthesizable synchronous design VHDL/Verilog codes that can be ported across multiple platforms and multiple implementations.
Take the same piece of Verilog or VHDL code and retarget to ASIC
cells with minimum or no code change.
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aramis
Joined: 07 Apr 2002
Posts: 103
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| 17 Jan 2003 16:17 |
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yes,
i agree with cbh1024
if your code is written "portable"
it can be synthesis either in FPGA or ASIC
(except the vendor component instance)
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ntxp
Joined: 29 May 2002
Posts: 57
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| 17 Jan 2003 16:59 |
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Did anyone tried the fpga vendor path to make ASIC?
Could share with us the price/lead time involved?
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corgan
Joined: 15 Jan 2002
Posts: 56
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| 17 Jan 2003 17:16 |
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Except write the fully synthesizable code,
beware of the SRAM part if you use internal SRAM for buffer/FIFO. You have to
take care of the timing to get correct result.
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prozess
Joined: 28 Sep 2001
Posts: 25
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| 18 Jan 2003 3:01 |
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| But I think the coding style of FPGA and ASIC are something diferent. So it may be for some reasons to write some code but they are not suitable for the other one.
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jkfoo
Joined: 17 May 2001
Posts: 37
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| 19 Jan 2003 5:24 |
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| You should minimize changes between FPGA and ASIC. Partition the design such that modifications are made only to necessary modules, eg. specific cores, RAM modules and clocking logic. Like what 'cbh1024' said, write your code as portable as possible. It will greatly minimize the verification effort.
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ntxp
Joined: 29 May 2002
Posts: 57
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| 19 Jan 2003 8:56 |
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Leon may be an good example of portable code for ASIC and FPGA uses. Of course, you have to design some technology primitive in a separate file that allow technology porting and maintenance easier.
Leon supports a lot of vendor tools and fpga/asic technologies through some technology/vendor dependent files, even though, the leon core is still very clean, and independent of (at least) technology uses.
ntxp
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calvinhorng
Joined: 18 Jul 2002
Posts: 103
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| 19 Jan 2003 9:53 GATEarray or standard cell |
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My personal study on the FPGA to ASIC migration will be based on
which technologies will be used.
Basically the gatearray product line offered by most of the foundry
will be 0.25um or above. Only the standard cell can have the state-of-the-art processing service.
As a result, timing will be a major concern. Of course the blockRAM in XILINX is hard to be included in the gatearray service though there
are lots of design house can do the netlist and RTL sign-off for you.
I do believe that there is still a great room to use the low-cost FPGA
such as those in ACTEL/@ltera/XILINX. So before jumping to ASI,
production volumn will be the major factor.
That is my personal opinion.
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ljkong
Joined: 18 Jul 2002
Posts: 128
Helped: 1
Location: P.R.C
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| 20 Jan 2003 2:19 |
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| good .
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