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solvall
Joined: 05 Apr 2005
Posts: 27
Helped: 9
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 31 Oct 2006 16:12 Avoid bit-blast I/O ports on Synopsys synthesis |
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I have a module as shown below,
in RTL
module ABC ( PTA, PTB);
input [3:0] PTA;
output PTB;
...
endmodule
after synthesis, netlist in Gate-level obtained from Synopsys Design Compiler
module ABC ( .PTA({PTA_3, PTA_2,PTA_1,PTA_0}) , PTB);
input PTA_3,PTA2,PTA_1,PTA_0;
output PTB;
....
endmodule
I don't like this type port " .PAT({PTA_3, PTA_2,PTA_1,PTA_0})"
How can I retain bused I/O ports in verilog netlist?
My Design compiler is ver 2005-09
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quan228228
Joined: 23 Mar 2006
Posts: 214
Helped: 13
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| 01 Nov 2006 3:09 Re: Avoid bit-blast I/O ports on Synopsys synthesis |
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By now, i havent seen this bused I/O ports in netlist.
Anyway, This type of ports is important ? Or can you tell us your motivation?
David
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aji_vlsi
Joined: 10 Sep 2004
Posts: 593
Helped: 69
Location: Bangalore, India
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| 01 Nov 2006 8:39 Re: Avoid bit-blast I/O ports on Synopsys synthesis |
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Hi,
DC has several variables that control the output format. A quick google search revealed this:
| Quote: |
verilogout_single_bit
When this variable is set to true, vectored ports (or ports that use
record types) are bit-blasted; if a port’s bit vector is N bits wide, it
is written out to theVerilog file as N separate single-bit ports.When
it is set to false, all ports are written out with their original data
types. The default is true.
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So try setting this variable to flase in your TCL script.
HTH
Ajeetha, CVC
www.noveldv.com
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solvall
Joined: 05 Apr 2005
Posts: 27
Helped: 9
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| 01 Nov 2006 13:48 Re: Avoid bit-blast I/O ports on Synopsys synthesis |
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I did have verilogout_single_bit set as false.
but the problem is still the same as follows,
module ABC ( .PTA({PTA3, PTA2,PTA1,PTA0}),...
)
input PTA3, PTA2, PTA1, PTA0;
endmodule
-------------------------------------
I want to retain PTA as bused ports.
module ABC ( PTA ,...
)
input [3:0] PTA;
endmodule
| aji_vlsi wrote: |
Hi,
DC has several variables that control the output format. A quick google search revealed this:
| Quote: |
verilogout_single_bit
When this variable is set to true, vectored ports (or ports that use
record types) are bit-blasted; if a port’s bit vector is N bits wide, it
is written out to theVerilog file as N separate single-bit ports.When
it is set to false, all ports are written out with their original data
types. The default is true.
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So try setting this variable to flase in your TCL script.
HTH
Ajeetha, CVC
www.noveldv.com |
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frankaurora
Joined: 03 Jun 2005
Posts: 11
Helped: 1
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| 05 Nov 2008 8:19 Re: Avoid bit-blast I/O ports on Synopsys synthesis |
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| you could use bus_naming_style =" %s[%d]" to fix it.
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