Case range with bitstream: VHDL

EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> Case range with bitstream: VHDL

Author

Message

lightofspace

Joined: 18 Oct 2006
Posts: 9

31 Oct 2006 11:43 vhdl case range

Hi there!!
I am stuck in a problem of CASE range, I have the following code:
----------------------------------------------------------------------------
input_data: IN std_logic_vector (7 downto 0);
output: OUT std_logic_vector (3 downto 0);
.
.
.
.
case input_data is
when "00000001" => output <= "0010";
when "10000000" to "11111111" => output <= "1000";
when others => output <= "1111";
end case;
----------------------------------------------------------------------------
I want to make case range facility to work with binary also, how can I do this?
thanks in advance,
ahmad

Google
AdSense
Google Adsense

31 Oct 2006 11:43 Ads

nand_gates

Joined: 19 Jul 2004
Posts: 907
Helped: 120

31 Oct 2006 14:11 vhdl case when range

In this special case you can write the case as follows...

Code:

case input_data is
when "00000001" => output <= "0010";
when "00000000" => output <= "1111";
when others => output <= "1000"; -- "10000000" to "11111111"
end case;

Other way is you generate this case statement using some kind of script!!

Code:

case input_data is
when "00000001" => output <= "0010";
when "10000000" |
"10000001" |
"10000010" |
...................
...................
"11111111" => output <= "1000";
when others => output <= "1111";
end case;