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Could you help me to generate these digital signal ?


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incol



Joined: 18 Jan 2005
Posts: 97


Post19 Oct 2006 8:45   

Could you help me to generate these digital signal ?


see Fig1, when A changes from high to low, after a short delay, B becomes to high;
when B changes from high to low, after a short delay, C becomes to high;
when C changes from high to low, after a short delay, A becomes to high;
and circulate follow this.

Use a clock and some digital gates to realize it, could some one help me?
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Fom



Joined: 10 Mar 2004
Posts: 778
Helped: 57
Location: Taiwan


Post19 Oct 2006 8:58   

Re: Could you help me to generate these digital signal ?


There is no Fig. 1.
What signals will make B and C change from high to low?
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incol



Joined: 18 Jan 2005
Posts: 97


Post19 Oct 2006 9:55   

Re: Could you help me to generate these digital signal ?


here is the Fig, and A,B,C are all the signals which I want the circuit to generate.

http://www.edaboard.com/viewtopic.php?p=709552#709552
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Post19 Oct 2006 9:55   

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nand_gates



Joined: 19 Jul 2004
Posts: 907
Helped: 120


Post19 Oct 2006 12:11   

Re: Could you help me to generate these digital signal ?


Here is one solution but its not generic.
May be ur looking this for 3 phase inverter??
Code:
module shifter (
   // Outputs
   A, B, C,
   // Inputs
   clk
   );
   input clk;
   output A, B, C;
   reg  [9:0] count = 0;
   assign      C = |count[9:8];
   assign      B = |count[5:4];
   assign      A = |count[1:0];
   
   always @(posedge clk)
     count <= {count[9:0],~|count[9:1]};
endmodule // shifter
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incol



Joined: 18 Jan 2005
Posts: 97


Post20 Oct 2006 2:14   

Re: Could you help me to generate these digital signal ?


Hi
Thank you for your help,could I use some nand or nor gates to realize it?


nand_gates wrote:
Here is one solution but its not generic.
May be ur looking this for 3 phase inverter??
Code:
module shifter (
   // Outputs
   A, B, C,
   // Inputs
   clk
   );
   input clk;
   output A, B, C;
   reg  [9:0] count = 0;
   assign      C = |count[9:8];
   assign      B = |count[5:4];
   assign      A = |count[1:0];
   
   always @(posedge clk)
     count <= {count[9:0],~|count[9:1]};
endmodule // shifter
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its_thepip



Joined: 15 Sep 2006
Posts: 44
Helped: 2


Post23 Oct 2006 5:44   

Re: Could you help me to generate these digital signal ?


do as same as above
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