help for GPS receiver architecture

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kaitlyn

Joined: 08 Jan 2005
Posts: 18

18 Oct 2006 9:56 help for GPS receiver architecture

hey guys,

Can you give me some idea about the GPS receiver architecture.

1, which one is most popular architecture in present research?
2, Which one is the commercial choice for the GPS receiver?

even through i read a lot of paper, i still can not get a conclusion.
please give me some clue!!!

Thx in advance!

Cheers

RFDave

Joined: 18 Feb 2004
Posts: 346
Helped: 45
Location: NE USA

19 Oct 2006 0:15 Re: help for GPS receiver architecture

Zero IF

Dave

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priyankguddu

Joined: 04 Feb 2005
Posts: 87
Helped: 6

19 Oct 2006 12:43 Re: help for GPS receiver architecture

BEST Realisation is using signle stage or double stage downconversion.

As per commercial use its better to downconvert the signal at suitable IF and gain and process it digitally.

If u go for zero IF the realisation has to be done in hardware or FPGA.

The choice is urs.

jwang

Joined: 19 Oct 2006
Posts: 1

19 Oct 2006 19:38 Re: help for GPS receiver architecture

Zero IF can be done easily on chip. The key issue is to remove the DC bias. One simple way is to add a coupling capacitor at the output of wodnconverter. At the center of the bandwidth. there is little energy because of BPSK modulation. If you set the high pass corner substantially (one order smaller) less than the chipping rate, you won't create too much distortion in signal and you can remove DC bias.

The key advantage of zero IF is the use of on-chip filter can be realized easily saving external component.

With low IF, the on-chip image rejection is typically 25 dB only.

kaitlyn

Joined: 08 Jan 2005
Posts: 18

20 Oct 2006 9:27 Re: help for GPS receiver architecture

Thanks a lot!!! very helpful. i think i will try to find the best specifications for the single conversion, the dual conversion or Zero IF architecture. then i can define my own reasonable specification.

here is my reference receiver for dual conversion: 19-mW 2.6mm2 with 8.5dB noise figures,an on-chip variable-gian channel fitler of 20dB image rejection . What do you think about this spec? do you guys do some better receivers?

RFDave

Joined: 18 Feb 2004
Posts: 346
Helped: 45
Location: NE USA

21 Oct 2006 1:58 Re: help for GPS receiver architecture

Gain Distribution?
AGC Level?
System Noise Figure?
LO Phase Noise?
Reciever system IIP3?
Reference Oscillator Frequency?
Filtering Bandwidth?

All relevant questions.

Dave
www.keystoneradio.com

kaitlyn

Joined: 08 Jan 2005
Posts: 18

23 Oct 2006 9:16 Re: help for GPS receiver architecture

for the measured result of this chip,
L1 band with chip NF 8.5dB,
Chip maximum gain 95dB,
AGC range >70dB,
image reject ratio 20dB in L1 band,
average phase noise -80dBc/Hz in-band,
filter bandwidth 2 MHz, 6-th order butterworth BPF
ADC 2-bit

that's what i know so far, feel free to give me some comments:)