what's the consequence of putting PAD in the middle of chip

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sophiefans

Joined: 12 Jun 2006
Posts: 48

11 Oct 2006 3:54 what's the consequence of putting PAD in the middle of chip

what's the consequence of putting PAD in the middle of chip?

Design rule says that the maxium distance from PAD to S/L guard ring is 200u. In another word, PAD must be putted around chip. In my opinion, this rule is relative to package. But if i don't package and will send the chip to test just after tapout,in this case, if i can put PAD in the middle of chip?

thanks in advance
sincerely,
sophiefans

sengyee88

Joined: 09 Oct 2006
Posts: 124
Helped: 20

11 Oct 2006 4:51 Re: what's the consequence of putting PAD in the middle of c

I believe in general, there is no harm to place pads at any place within the chip but we always avoid doing this. As u may need to consider:
1. If there is any difficulty when doing wire bonding. Wire bond to a pad at the middle of the chip requires longer wire bonding, it is easier to break and higher chance that it may cross over other wire bondings.
2. When doing wire bonding, certain stress is applied to the IC. If it is located at the middle, stress may proporgate to entire IC.
3. If your IC is flip-chip.

If the pads are just for EWS probing, not for wire bonding, i think it will still be ok.