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its_thepip
Joined: 15 Sep 2006
Posts: 44
Helped: 2
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 10 Oct 2006 15:41 why reverse biased juction nmos |
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Hi
In MOS , there are two pn junctions formed
1) Between n+ Source and PSubstrate
2)Between n+ Drain and PSubstrate
In Kang,I read that these junctions are always reverse biased ...
How does this happen ??
If the junction 1 is to be reverse biased , then source has to be at a higher potential than the Psubstrate
But to eliminate the body effect , we short the substrate and source....
In this situation , how does the source-substrate be reversie biased ???
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sengyee88
Joined: 09 Oct 2006
Posts: 124
Helped: 20
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10 Oct 2006 16:28 mos substrate biasing |
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| Quote: |
In MOS , there are two pn junctions formed
1) Between n+ Source and PSubstrate
2)Between n+ Drain and PSubstrate
In Kang,I read that these junctions are always reverse biased ...
How does this happen ??
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This is the reason that normally bulk of PMOS always connected to supply while bulk of NMS always connected to lowest supply (VSS).
| Quote: |
If the junction 1 is to be reverse biased , then source has to be at a higher potential than the Psubstrate
But to eliminate the body effect , we short the substrate and source....
In this situation , how does the source-substrate be reversie biased ???
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Normally we only short substrate and source for differential pair, as we want to avoid Vth fluctuation due to change of Vsb and avoid supply noise directly coupled to differential pair via substrate. In this case, source-substrate will neither be reversed biased nor forward biased.
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bunalmis
Joined: 03 Jan 2003
Posts: 254
Helped: 5
Location: Turkey
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10 Oct 2006 16:50 forward biasing substrate source drain nmos |
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we short the substrate and source....
In this situation , how does the source-substrate be reversie biased ??? |
This is valid for three terminal MOS.
If you want reverse bias you need four terminal MOS.
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zxcynosure
Joined: 22 Dec 2005
Posts: 7
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10 Oct 2006 17:02 source biasing mos |
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in real fact. all mos are 4 terminal devices. generally, there are 2 operating.
(use nmos for example)
1. source and bulk(substrate or pwell) connect together. based on standard cmos process, there are not isolated P-well, so, bulk is directly connected to substrate together with source, without body effect.
2. bulk connects to lowest votlage(lower than source, otherwise, bulk source pn junction will forward bias). this can be seen in source follower, switch application et al.
In all cases, PN junction will not forward bias, but will zero bias or reverse bias
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