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Message |
davyzhu
Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental
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 22 Sep 2006 10:27 ncsim force |
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Hi all,
I want to write a Tcl in ncsim to do below work.
1. stop when $signal is 1
2. set the lock to force stop only stop once
3. force $other_signal
4. continue run
5. force $other_signal back
6 continue run
But ncsim said "cannot run command executed from a stop -execute script".
Any suggestions, thanks!
| Code: |
#----- Tcl begin ---
set lock 0
stop -silent -name stop_name -cont -cond { [value $CLK] == 1 && $signal ==1 && $lock == 0} -exec {
set lock 1
force other_signal = 8'b10010000
run 50us
force other_signal = 8'b10001010
}
run 50us
#----- Tcl end --- |
Best regards,
Davy
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Shurik
Joined: 15 Jul 2004
Posts: 162
Helped: 12
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22 Sep 2006 14:24 forces in ncsim.log |
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| Is it for simulation of verilog code?
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aji_vlsi
Joined: 10 Sep 2004
Posts: 640
Helped: 72
Location: Bangalore, India
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23 Sep 2006 2:33 force ncsim |
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Hi,
Not sure if stop inside a stop is allowed, if so the following should work:
| Code: |
#----- Tcl begin ---
set lock 0
stop -silent -name stop_name -cont -cond { [value $CLK] == 1 && $signal ==1 && $lock == 0} -exec {
set lock 1
force other_signal = 8'b10010000
stop -time -relative 50 us -cont -exec { force other_signal = 8'b10001010}
}
run 50us
#----- Tcl end --- |
If this doesn't work let me know, we can find some thing else.
Regards
Ajeetha, CVC
Contemporary Verification Consultants Pvt Ltd. http://www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar
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davyzhu
Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental
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23 Sep 2006 3:09 ncsim stop simulation |
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Hi aji_vlsi,
Thanks a lot, and I will try your method next week 
Hi Shurik,
Yes, it's Verilog simulation.
Best regards,
Davy
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23 Sep 2006 3:09 Ads |
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Shurik
Joined: 15 Jul 2004
Posts: 162
Helped: 12
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23 Sep 2006 14:33 force ncsim |
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Hi davyzhu!
I am not using the Tcl script for simulation.
I write testbench which control the simulation.
Best regards.
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yln2k2
Joined: 22 Sep 2006
Posts: 89
Helped: 10
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25 Sep 2006 3:41 force value ncsim |
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Hi ,
If possible try to do the same in testbench ( if you have visibility of the signal ...) .
This will increase perfomance than using Tcl .
Thanks & Regards
yln
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aji_vlsi
Joined: 10 Sep 2004
Posts: 640
Helped: 72
Location: Bangalore, India
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25 Sep 2006 6:08 ncsim assertions |
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| yln2k2 wrote: |
Hi ,
If possible try to do the same in testbench ( if you have visibility of the signal ...) .
This will increase perfomance than using Tcl .
Thanks & Regards
yln |
Good point. Given that it is Verilog, visibility is not an issue at all. EVen if you were using VHDL, one can use signal_spy/nc_mirror/hdl_xmr feature to achieve the same.
Ajeetha, CVC
www.noveldv.com
Contemporary Verification Consultants Pvt Ltd. http://www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar
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