Verification of analog designs

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chviswanadh

Joined: 02 May 2005
Posts: 482
Helped: 188
Location: Bangalore

19 Sep 2006 14:04 Verification of analog designs

Hello,

Is it right way to verify analog designs at varous PVT and design corners?

Eventhough the specifications are verified at simulation stage(at PVT corners) is it going to ensure an error free design on silicon.

If it is not can some body give me the right way to verify the designs

Are these results going to be simulator dependant??

Please give me some inputs on this.

Thanks
chvswanadh

shaikhsarfraz

Joined: 08 Aug 2006
Posts: 309
Helped: 19

19 Sep 2006 14:24 Re: Verification of analog designs

Hi,
Verification mainly deals with corner verification.
However it is the job of Verification engineer to find the loop holes in the circuit even if the circuit is passing all the process corners.

If you want to verify your circuit more conservatively then go for Monte Carlo analysis with variation in FOX and TOX thickness , and some other variations.

If your circuit is passing Monte Carlo analysis then you can be rest assured that if there is any failure of circuit thats due to FAB limitation.

Thanks
sarfraz

piao

Joined: 12 Feb 2003
Posts: 223
Helped: 7

19 Sep 2006 15:04 Verification of analog designs

verification will deal with the different combination of the PVT.

chviswanadh

Joined: 02 May 2005
Posts: 482
Helped: 188
Location: Bangalore

19 Sep 2006 15:48 Re: Verification of analog designs

Hello Piao,

Thanks for your reply. I know that verification is done at combination of PVT corners. My question was is it going to make sure an error free design on silicon.

To Shaik Sarfraz,

Thanks for the reply. I can understand your point but what do you mean to say loop holes. To give more clarity on my question, I was talking about the pre layout verification.

Thanks
chviswanadh

shaikhsarfraz

Joined: 08 Aug 2006
Posts: 309
Helped: 19

20 Sep 2006 4:51 Re: Verification of analog designs

Hi,
For pre layout verification to make your design error free, the only thing I can suggest is to take into consideration the parasictic and routing capacitance. This will help in knowing the performance of the system when it will be drive some other load.

thanks
sarfraz

chviswanadh

Joined: 02 May 2005
Posts: 482
Helped: 188
Location: Bangalore

20 Sep 2006 14:52 Re: Verification of analog designs

Hello Sarfraz,

How can we estimate the parasitics of routing?

because at the simulation stage we dont know how much of these parasitics come into picture after layout.

Thanks
chviswanadh

chang830

Joined: 11 Feb 2006
Posts: 263
Helped: 11

21 Sep 2006 8:47 Re: Verification of analog designs

chviswanadh wrote:

Except for the PVT corners verifications, the statisical mismatch analysis is key part for the sucess for the deisgn. We always pass it with all PVT corners and guranteed it meet the spec in WCS.Then the mismatch analysis will be done to investiagate the robustness for the design vs. the sattiscal mismatchings.

After the pre-sim designs, we need to verify it in post-simulations. The package parasitics is alos counted into the design. For the mixed design, it is more complicated for the noise considerations, it is selodom can be modeld in design.

Then, we also need to check the layout carefully to investigate the potetional risks for the EOS(electrical over stress) and EMI etc...Even it passed the DRC ruls, this investigations is also necessary for long term reliability.

So,the specifications are verified at simulation stage(at PVT corners) is just one of the key parts to ensure an error free design on silicon.

Thanks

chviswanadh

Joined: 02 May 2005
Posts: 482
Helped: 188
Location: Bangalore

21 Sep 2006 13:51 Re: Verification of analog designs

hello chang830,

Thanks for the reply.
I didn't understand couple of things in your reply. What do you mean by statistical analysis. Secondly what is WCS.

You said we need to consider circuit parasitics after post simulation. Is there a way to estimate the paracitics.

Thanks
chviswanadh

chang830

Joined: 11 Feb 2006
Posts: 263
Helped: 11

22 Sep 2006 6:20 Re: Verification of analog designs

chviswanadh wrote:

In normally, we did not do the Monte Carlo analysis for the design. We ask the design meet the spec at WCS, here WCS is the worst condition case, i.e. the worst one for the combined PVT cases. The statisical analysis is always for the mismatch analysis, e.g., you can perform the Monte Carlo analysis to investiagte the sensitivity of the design versus the mismatch.

About the parasitics, the RC extarction can give you the parasitics value and you can use the post-lyaout netlist for the simulation. As for the estimate of the parasitics in pre-sim, you can try to add some caps in the interesting nodes in pre-sim, which can give you a quick verification for your design. Another one is if your design is based on a previous one which assume has a good design report/memo containing the compliance data for the pre-sim and post-sim. You can refer it in the design phase.

shaikhsarfraz

Joined: 08 Aug 2006
Posts: 309
Helped: 19

22 Sep 2006 6:54 Re: Verification of analog designs

Hi,
As you have asked that how to calculate the routing capacitance while designing the Schematic.

This things are learnt with experience. You can take a worst case routing capacitance and simulate using this value.

thanks
sarfraz

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chviswanadh

Joined: 02 May 2005
Posts: 482
Helped: 188
Location: Bangalore

23 Sep 2006 5:57 Re: Verification of analog designs

Hello Chang,

Thanks for the information that is really useful.

Now I have an issue finding the stability of a switching regulator.

If you have an idea abt this please let me know how to perform the stability analysis.

Thanks
chviswanadh

chang830

Joined: 11 Feb 2006
Posts: 263
Helped: 11

25 Sep 2006 3:27 Re: Verification of analog designs

chviswanadh wrote:

It is a bit compliticated about the stability analysis for the switching regulator.The coventional small signal loop analysis is not easily appliied to switching regulator.

I remembered I ever part in a design review on the siwtching regulator in a large semiconductor corporation. The designer used the transient analysis to check the stability. You can try to use the step response to assess the stabilty.

Hope it helps.

chviswanadh

Joined: 02 May 2005
Posts: 482
Helped: 188
Location: Bangalore

25 Sep 2006 8:50 Re: Verification of analog designs

Hello chang,

I have a doubt here. Transient is done over a period of time where the input stimulus is time varying. But the small signal analysis is done at steady state.

So how can you find the operating point through the transient and even stability?

Regards
chviswanadh

shaikhsarfraz

Joined: 08 Aug 2006
Posts: 309
Helped: 19

25 Sep 2006 11:02 Re: Verification of analog designs

hi,
I donnot know whether transient analysis can be done to find the stability.
Transient analysis is a large signal analysis. The operating points are found by the biasing that is provided for the circuit.

thanks
sarfraz