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newcpu
Joined: 30 Oct 2005
Posts: 80
Helped: 2
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 08 Sep 2006 10:02 Formality unmatched register |
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Hi all,
When I run formality between RTL and netlist after synthesis, there are some registers unmatched. Could anyone tell me some possible reasons?
Best Regards,
newcpu
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funster
Joined: 30 Jun 2005
Posts: 235
Helped: 12
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| 09 Sep 2006 5:01 Re: Formality unmatched register |
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perhaps your synthesis script allow DC eliminate some
unused registers, these registers has no relationship with
outputs.
best regards
| newcpu wrote: |
Hi all,
When I run formality between RTL and netlist after synthesis, there are some registers unmatched. Could anyone tell me some possible reasons?
Best Regards,
newcpu |
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leeenghan
Joined: 28 Dec 2004
Posts: 125
Helped: 7
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| 10 Sep 2006 4:24 Formality unmatched register |
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Hi,
The current generation of synthesis tool is very powerful; they can find FF that are redundant, and simplify the logic that lead to the removal of the FF. This is common in IP where the user do not use many of the modes.
Regards,
Eng Han
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foster_cn
Joined: 14 Jan 2003
Posts: 74
Helped: 2
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| 14 Sep 2006 6:19 Formality unmatched register |
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| is there any book that focus on formality? I feel there are few material talk about formality debug practice.
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darylz
Joined: 24 Mar 2005
Posts: 132
Helped: 4
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| 14 Sep 2006 6:25 Formality unmatched register |
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| just get funciton matched
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rameshsuthapalli
Joined: 27 Jun 2006
Posts: 163
Helped: 19
Location: bangalore,india
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| 14 Sep 2006 6:33 Formality unmatched register |
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Hi All,
The DesignCompiler from 2005.09 onwards giving a default file in work directory with name default.svf use that svf in the formality will resolve the above problem. the svf contains the guidense for the formality.
regards
Ramesh.s
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kbulusu
Joined: 23 Apr 2003
Posts: 122
Helped: 7
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| 06 Oct 2006 1:30 Re: Formality unmatched register |
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| is ur register mapping correct? Check ur mapping and see if any unmatched registers exists between golden and revised. If there are, then you need to map them before u proceed for verification. u should also mimic the same synthesis env in ur formal verification env. if u r driving some ports/pins/nets to constant, u should do the same in FV . also at what stage are u doing FV? if after scan insertion, u have to tie the Scan eenable and test mode to "0". IF you are doing re-timing, check if ur FV tool has the same...if you ahve design ware multipliers in the code, then any FV tool will flunk..as synopsys recommends it can be verified using simulation...Most FV tools have the options which when used will create the same synthesis env. recently I have seen couple of bugs/false failures with formality. so check another version or Verplex or Quartz formal from magma..
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kevine
Joined: 03 Jul 2006
Posts: 8
Helped: 1
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| 22 Oct 2006 9:34 Formality unmatched register |
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agree with Ramesh.s.
the reasons of many problems can be found in .svf file .U can also observe the match results of FM and compare which parts r matched by name or signature analysis,and then go to find the reasons
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sumit_techkgp
Joined: 01 Apr 2007
Posts: 135
Helped: 3
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| 16 Apr 2007 13:38 Formality unmatched register |
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During synthesis dc has removed those unused registers whatever has been written in RTL. Please save a .svf file during synthesis and read it out with formality. This problem will go away.
Sumit
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shashi_dhar123
Joined: 30 Mar 2007
Posts: 14
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| 16 Apr 2007 20:10 Re: Formality unmatched register |
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| i also want to know abt it
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