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Memory data file: Keil
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junaid



Joined: 06 Jul 2006
Posts: 11
Post04 Sep 2006 13:39   

Memory data file: Keil
Hi Folks,

I am using Keil compiler for MCS-51 target. I need an initialisation file for RAM(data memory).
I think the initialisation file for ROM is .hex file generated by compiler.

I have got program which move data between memories and I could generate . hex file and run on keil simulator.

So can anybody tell me how to generate or get the file for data memory?
I need it for VHDL model of 8051.

Thanx in advance,
Junaid
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Post04 Sep 2006 13:39   

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kordix



Joined: 18 Jan 2006
Posts: 64
Helped: 5
Post05 Sep 2006 3:26   

Re: Memory data file: Keil
I don't understand your question!
but hope this will help u:

I don't even remember where did i get it!

Sorry, but you need login in to view this attachment
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kordix



Joined: 18 Jan 2006
Posts: 64
Helped: 5
Post05 Sep 2006 3:28   

Memory data file: Keil
this is a VHDL design for the 8051.
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junaid



Joined: 06 Jul 2006
Posts: 11
Post05 Sep 2006 8:36   

Re: Memory data file: Keil
Hi Kordix,

Thanx for that stuff that will be helpfull for me.
Actually I am looking for generation hex file for data memory in Keil compiler.

I need to have a file to inilialise data memory.


Regards,
Junaid
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bis_



Joined: 21 Jun 2006
Posts: 50
Helped: 13
Post05 Sep 2006 10:36   

Re: Memory data file: Keil
The initialization of the data variables in RAM and XRAM is done at the startup phase of the MCU51 program based on the datas stored in ROM for "initialized variables" segment by the linker. There are no need to initialize it by FPGA configuration. But if you like it: the data can be resolved directly from .hex file using proper offsets for the initialization segment. Look at file "startup.a51" and output linker map files.

bis
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junaid



Joined: 06 Jul 2006
Posts: 11
Post05 Sep 2006 12:46   

Re: Memory data file: Keil
Hi Bis,

Thanx a lot. You cleared my question. So the compiler explicitly doesn't generate .hex file for RAM n XRAM.

Actually I need it for initialising RAM in VHDL model using file I/O. If you have info. on this it would be very nice.

Regards,
Junaid
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