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siva_7517
Joined: 16 Jan 2006
Posts: 136
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 16 Aug 2006 8:36 synopsys design compiller warning |
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Hi,
I have a warnig from synopsys design compiler as below:
Warning: /projects/rfid/design/dspuhf/dfII/newdesign/8point/system_fft_synopsys/withoutdft/
full_fft.v:252: signed to unsigned assignment occurs. (VER-318)
this warning occurs after i read it in design compiler.
this is the example code:
assign ft1a_re = $signed(pfs1_re) + $signed(pfs5_re);
assign ft1a_im = $signed(pfs1_im) + $signed(pfs5_im);
is there anything of wrong in this code which makes a warning in synopsys?
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aji_vlsi
Joined: 10 Sep 2004
Posts: 593
Helped: 69
Location: Bangalore, India
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| 16 Aug 2006 8:56 Re: synopsys design compiller warning |
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Show us the declaration of these 2 wires:
ft1a_re , ft1a_im;
Looks like they are unsgined (default in Verilog)
Ajeetha, CVC
www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
h**p://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar
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siva_7517
Joined: 16 Jan 2006
Posts: 136
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| 16 Aug 2006 9:29 Re: synopsys design compiller warning |
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Below is my example of coding:
module stage0_1 ( fps0_re, fps0_im, fps2_re, fps2_im, fps4_re, fps4_im, fps6_re, fps6_im, zf1a_re, zf1a_im, zf1b_re, zf1b_im, zf2a_re, zf2a_im, zf2b_re, zf2b_im);
parameter bit = 16;
input [bit-1:0] fps0_re;
input [bit-1:0] fps0_im;
input [bit-1:0] fps2_re;
input [bit-1:0] fps2_im;
input [bit-1:0] fps4_re;
input [bit-1:0] fps4_im;
input [bit-1:0] fps6_re;
input [bit-1:0] fps6_im;
output [bit-1:0] zf1a_re;
output [bit-1:0] zf1a_im;
output [bit-1:0] zf1b_re;
output [bit-1:0] zf1b_im;
output [bit-1:0] zf2a_re;
output [bit-1:0] zf2a_im;
output [bit-1:0] zf2b_re;
output [bit-1:0] zf2b_im;
assign zf1a_re = $signed(fps0_re) + $signed(fps4_re);
assign zf1a_im = $signed(fps0_im) + $signed(fps4_im);
assign zf1b_re = $signed(fps2_re) + $signed(fps6_re);
assign zf1b_im = $signed(fps2_im) + $signed(fps6_im);
assign zf2a_re = $signed(fps0_im) - $signed(fps4_im);
assign zf2a_im = $signed(fps4_re) - $signed(fps0_re);
assign zf2b_re = $signed(fps2_im) - $signed(fps6_im);
assign zf2b_im = $signed(fps6_re) - $signed(fps2_re);
endmodule
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aji_vlsi
Joined: 10 Sep 2004
Posts: 593
Helped: 69
Location: Bangalore, India
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| 16 Aug 2006 10:32 Re: synopsys design compiller warning |
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Declare your output as wire signed:
wire signed [bit-1:0] f1a_re;
wire signed [bit-1:0] f1a_im;
That should get you going. Also consider using lint tools such as Leda to avoid finding these at DC time (usually my customers tell me that DC is more expensive, takes longer to run etc. I recommend Lint tools such as Leda/Spyglass etc. to them).
Ajeetha, CVC
www.noveldv.com
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