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hariharan4000
Joined: 04 Dec 2005
Posts: 18
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 13 Aug 2006 6:26 setup/hold |
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guys! i want to know wats negative setup and holdtimes.
plz explain.if there is any pdf or link it would be fine.
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mpatel
Joined: 25 Aug 2005
Posts: 54
Helped: 4
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| 16 Aug 2006 13:59 Re: setup/hold |
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| hariharan4000 wrote: |
guys! i want to know wats negative setup and holdtimes.
plz explain.if there is any pdf or link it would be fine. |
setup time is time taken by circuit to start the operation.
hold time is time taken by circuit to provide output after operation get finished.
Negative setup/hold time means these time does not fit in the design criteria which you selected and these times exceeds than provided. If you reduce design frequency, setup time may be solved.
Read following post, which gives good idea how to solve this problem.
http://www.edaboard.com/ftopic185821.html
You can refer xilinx documentation on synthesis also, which may give me some information. visit documentation section on ww.xilinx.com
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xiexie57
Joined: 04 Jul 2006
Posts: 32
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| 18 Aug 2006 2:48 setup/hold |
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chek this one "Calculating the setup and hold times at the pins of a chip":
h**p://www.arl.wustl.edu/~jaf/hardware/chip-setup-hold-time-calculation.html
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