aji_vlsi
Joined: 10 Sep 2004
Posts: 593
Helped: 69
Location: Bangalore, India
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 12 Aug 2006 9:15 Re: what does the SCV_ERROR mean? |
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Hi,
It means that your constraints are conflicting and hence the solver is unable to solve them. Show us the piece of code that has your constraints.
BTW - do you use with NC? It may have some constraint debugger to assist. I have heard that Specman has a decent constraint debugger but that works on e-code, perhaps Cadence has ported it for SCV as well.
Also, did you consider using SystemVerilog for the same? Not that your results will be different - if you over-constrain, any tool will give you such error. The ease of adoption is better with SystemVerilog.
HTH
Ajeetha, CVC
www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 h**p://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar
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