Rules | Recent posts | topic RSS | Search | Register  | Log in

How to visualize clock relations?

 
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Author Message
steven852



Joined: 24 Apr 2005
Posts: 105
Helped: 1


Post10 Aug 2006 0:38   How to visualize clock relations?

Hi,

I want to know what effects are when creating a clock source and a generated clock and then set setting latency, uncertainty, etc. Is there a GUI tool to visualize what effects are? Basically I want to solve the setup timing violation in SoC Encounter by looking at the launch delay and capture delay (the data delay is fixed). I am not sure what commands can help to set these two delay in order to fix setup violations.

Thanks.
Back to top
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Page 1 of 1 All times are GMT + 1 Hour


Abuse
Administrator
Moderators
topic RSS 
sitemap