Rules | Recent posts | topic RSS | Search | Register  | Log in

how to remove backlash from DC generated netlist

 
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Author Message
dcreddy1980



Joined: 03 Dec 2004
Posts: 129
Helped: 8
Location: Munich, Germany


Post09 Aug 2006 13:04   how to remove backlash from DC generated netlist

How can we remove backlashes from the Design compiler generated netlist.

for example : wire \x[0],\x[1] where x is a 2-bit vector

Regards,
dcreddy
Back to top
Atre



Joined: 15 Jul 2002
Posts: 102
Helped: 4
Location: Eindhoven, the Netherlands


Post09 Aug 2006 23:19   Re: how to remove backlash from DC generated netlist

dcreddy1980 wrote:
How can we remove backlashes from the Design compiler generated netlist.

for example : wire \x[0],\x[1] where x is a 2-bit vector

Regards,
dcreddy


Hello,

You can use define_name_rules/change_names to clean it that's what you really want to do.
Back to top
rameshsuthapalli



Joined: 27 Jun 2006
Posts: 163
Helped: 19
Location: bangalore,india


Post10 Aug 2006 4:28   how to remove backlash from DC generated netlist

Hi dcreddy1980,

the problem is occered bcz of the wrong declaration of the evironmental variable in DC.
plz set the "verilogout_single_bit" veriable to "false".
then this problem will disapears.

regards
Ramesh.S
Back to top
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Page 1 of 1 All times are GMT + 1 Hour


Abuse
Administrator
Moderators
topic RSS 
sitemap