aji_vlsi
Joined: 10 Sep 2004
Posts: 593
Helped: 69
Location: Bangalore, India
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 11 Aug 2006 12:30 Re: listing all ifdef parameters used in design |
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Commercial EDA tools should be able to do this. However, since these are pre-processor directives, it is possible that it in non-trivial to get that list. One tool that I can think of is a Lint tool such as Leda from Synopsys. They usually don't optimize your design and hence might preserve these.
Other options are:
1. There is a VPP - Verilog pre-processor, opensource in web, may be you can h(at)ck it to get this.
2. Icarus/Cver are opensource Verilog simulators - you may be able to h(at)ck them to do this for you.
Let me know how it goes.
Ajeetha, CVC
www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar
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