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alerta
Joined: 25 Jul 2005 Posts: 18
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07 Aug 2006 23:53 question about verilog behavioral model |
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the following is a pragraf of Verilog Behavioral Model of Synchronous Mobile SDRAM
task write_task;
begin
begin: write_op
integer i, j, k;
reg [`BIT] tmp_reg;
integer bank_id;
reg [8*8:1] str;
if(~burst_type)
increment_read;
else
interleave_read;
begin: write_seq
for(i = 0; i < WBL; i = i+1)
begin // { for loop
begin
.......
I don't know the meaning of "write_op " and "write_seq", they seems no use,
are they only a mark ,or the standard?
who can tell me,thanks
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asic_bh
Joined: 26 Jul 2006 Posts: 8
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08 Aug 2006 0:26 Re: question about verilog behavioral model |
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| "write_op " and "write_seq", are just the name given to the block of code (from begin to end). This is useful when u want disable the execution of that block of code which is done by saying disable block name. That can be enabled again
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tigerajs
Joined: 08 Feb 2006 Posts: 30
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08 Aug 2006 12:38 Re: question about verilog behavioral model |
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| it is a process
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naveen reddy
Joined: 02 Jun 2005 Posts: 25
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09 Aug 2006 10:42 Re: question about verilog behavioral model |
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hai
This is the concept of named blocks in verilog
You can name a block and disable a named block
eg >> begin:write_op
write_op is the name given to this particular block
You can have any number of named blocks in your design with a unique name
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anilkumarv
Joined: 23 Apr 2006 Posts: 45 Helped: 1
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10 Aug 2006 11:21 Re: question about verilog behavioral model |
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| They are basically the names given to the particular block
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chviswanadh
Joined: 02 May 2005 Posts: 482 Helped: 188 Location: Bangalore
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10 Aug 2006 13:30 Re: question about verilog behavioral model |
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| Those are just the labels of the process. In small codes one may not find it much useful but while writing large code where u might have many process blocks (which may look similar) it is of great use to give the labels. these are for users reference only.
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