| Author |
Message |
s_mahale
Joined: 28 Jul 2006
Posts: 7
Helped: 1
|
 07 Aug 2006 9:21 floor planning |
|
|
|
|
can any1 help me out in explaining the eact work of FLOOR PLANNING?
wat is done in tat?
|
|
| Back to top |
|
 |
Thinkie
Joined: 26 May 2005
Posts: 174
Helped: 14
|
| 07 Aug 2006 9:44 floor planning |
|
|
|
|
Floorplanning is the process of defining the chip-size, placing the macrocell and placing I/O pads.
At this stage you can do an estimate for routing requirements etc.
|
|
| Back to top |
|
|
mmike
Joined: 04 Jun 2006
Posts: 553
Helped: 19
|
| 11 Aug 2006 20:32 Re: floor planning |
|
|
|
|
| It is optimised way of putting things together ... to save space and accommodate more items ...
|
|
| Back to top |
|
|
steven852
Joined: 24 Apr 2005
Posts: 105
Helped: 1
|
| 12 Aug 2006 23:04 Re: floor planning |
|
|
|
|
| Floor planning also includes power stripes, vias, and partitioning.
|
|
| Back to top |
|
|
rajesh9999
Joined: 19 Oct 2005
Posts: 44
Helped: 2
|
| 13 Aug 2006 2:41 Re: floor planning |
|
|
|
|
Floorplanning is the process of creating core and IO areas with rows defined in the core area. Each row will be divided into a minimum unit of area called SITE. Any placed cell will occupy one or more of these sites. The floorplan can be created as soon as the netlist and the LEF is read into the backend tool. After the foorplan the you can get parameters like area of the die, utilization etc.
Sometimes rough placement of blocks is also included in the floorplan. For example, ameoba placement in SOC-E is also part of floorplan. Hope this helps
|
|
| Back to top |
|
|
