Rules | Recent posts | topic RSS | Search | Register  | Log in

setup hold timing during post layout simulations using ncsim

 
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Author Message
sami_1



Joined: 08 Jun 2006
Posts: 3
Helped: 1


Post03 Aug 2006 13:37   setup hold timing during post layout simulations using ncsim

When doing post layout simulations, ncsim is given both sdf and library_model.v files. The library_model.v file has all the models + timings for the cells in the libraray. The default is 1ns for both setup and hold. When doing simulations using ncsim, are sdf values taken into acccount only and info in library_model.v discarded ? I need to find out how both the files are used and where do the setup hold timing requirements for the Flops come from during post layout simulations
Thanks
Back to top
anant



Joined: 20 Sep 2004
Posts: 31
Helped: 3


Post10 Aug 2006 5:52   setup hold timing during post layout simulations using ncsim

all the timing related information is present in sdf file "Delays: module path, device, interconnect, and port Timing checks: setup, hold, recovery, skew, width, and period." when you do back annotation the timming information from sdf file is used.
Back to top
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Page 1 of 1 All times are GMT + 1 Hour


Abuse
Administrator
Moderators
topic RSS 
sitemap