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vcnvcc
Joined: 21 Jul 2006
Posts: 88
Helped: 1
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 03 Aug 2006 7:16 Timing violation in memory Block |
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In my design, in one of the fifo block in instantiating inbuilt RAM. Now Tool (Quatus tool, Fpga Based design) shows something like this
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Now could you suggest me what to do for this problem??
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shankarmit
Joined: 22 Jun 2005
Posts: 187
Helped: 8
Location: India
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| 07 Aug 2006 12:13 Re: Timing violation in memory Block |
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fpga based design has memory that can't operate above certain frequency.. ensure that your dont set the frequency above that while generating fifo using coregen...
Check the documents for frequencies...
Regards
Shankar
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vcnvcc
Joined: 21 Jul 2006
Posts: 88
Helped: 1
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| 08 Aug 2006 8:37 Re: Timing violation in memory Block |
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thanks shankar for ur responce..
My board on which the fpga is 50 Mhz. and my design in fpga works on 60 Mhz...Though it is issue of 2 clock domain, the care has been taken for the same..
But what i am suspecting is.........while writing in to that fifo which has instantiated RAM(@ 60 Mhz) or reading from (@ 50 Mhz) , some amount of data gets corrupts...this is my assumption.....synchronizers are added whereever required..
Please suggest something.......
Regards.
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shankarmit
Joined: 22 Jun 2005
Posts: 187
Helped: 8
Location: India
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| 10 Aug 2006 6:33 Re: Timing violation in memory Block |
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i am little bit confused that.. your board is operating at 50 Mhz means ... the clock to fpga is 60 Mhz or 50 Mhz.. ( means the crystal clock oscillator)...
Added after 2 minutes:
As you say the fifo data gets corrupted. fifo get corrupted only when the length of fifo is minimum and it starts overwriting... take fifo separately and test it with input 60 mhz and output 50 mhz.. the fifo length is most important... check that...
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vcnvcc
Joined: 21 Jul 2006
Posts: 88
Helped: 1
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| 14 Aug 2006 10:45 Re: Timing violation in memory Block |
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thanks again shankar,
About 2 clocks,
In my design which is loaded in to fpga in working 60 and 50 Mhz. working on ip, its one side works at 60 Mhz and other side at 50 Mhz.
Now components mounted on board all works at 50 Mhz. And fpga has 2 clock pins one for 50 n other for 60 mhz.
And what i said abt fifo data gets corrupted is my assumptions. actually it is whole systems, so it can be a software problem also. we are just assuming n getting a pic in mind.....if you know any method for the same plz let me know......
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mpatel
Joined: 25 Aug 2005
Posts: 54
Helped: 4
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| 16 Aug 2006 13:27 Re: Timing violation in memory Block |
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| vcnvcc wrote: |
thanks again shankar,
About 2 clocks,
In my design which is loaded in to fpga in working 60 and 50 Mhz. working on ip, its one side works at 60 Mhz and other side at 50 Mhz.
Now components mounted on board all works at 50 Mhz. And fpga has 2 clock pins one for 50 n other for 60 mhz.
And what i said abt fifo data gets corrupted is my assumptions. actually it is whole systems, so it can be a software problem also. we are just assuming n getting a pic in mind.....if you know any method for the same plz let me know...... |
Well, I worked for multi-clock domain FPGA design at 125 MHz, but it is somewhat unclear for me:
1. Do you refer 50 & 60 MHz as read/write clock for FIFO?
if yes then you have to make FIFO control block to handle read/write enable regarding your clock frequency.
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