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brain123
Joined: 02 Aug 2006
Posts: 8
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 02 Aug 2006 16:21 difference between fpga and cpld |
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| Can anyone tell me the differences between an FPGA & CPLD in terms of architecture, power, internal routing. etc.
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bauer
Joined: 21 Jun 2006
Posts: 212
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02 Aug 2006 16:47 difference between cpld asic fpga |
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A field programmable gate array (FPGA) is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinational functions such as decoders or simple math functions. In most FPGAs, these programmable logic components (or logic blocks, in FPGA parlance) also include memory elements, which may be simple flip-flops or more complete blocks of memories.
A hierarchy of programmable interconnects allows the logic blocks of an FPGA to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. These logic blocks and interconnects can be programmed after the manufacturing process by the customer/designer (hence the term "field programmable") so that the FPGA can perform whatever logical function is needed.
FPGAs are generally slower than their application-specific integrated circuit (ASIC) counterparts, can't handle as complex a design, and draw more power. However, they have several advantages such as a shorter time to market, ability to re-program in the field to fix bugs, and lower non-recurring engineering costs. Vendors can sell cheaper, less flexible versions of their FPGAs which cannot be modified after the design is committed. The development of these designs is made on regular FPGAs and then migrated into a fixed version that more resembles an ASIC. Complex programmable logic devices, or CPLDs, are another alternative.
CPLD stands for Complex Programmable Logic Device. It is a programmable logic device with complexity between that of FPGAs and PALs, and architectural features from both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations.
Features in common with PALs:
* Non-volatile configuration memory. Unlike many FPGAs, an external configuration PROM isn't required, and the CPLD can function immediately on system start-up.
* For all but the largest devices, routing constrains most logic blocks to have input and output signals connected to external pins (little opportunity for internal state storage or deeply layered logic).
Features in common with FPGAs:
* Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.
* Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly-used functions (such as integer arithmetic).
The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD. The differences in architectural approach become more apparent farther from this intermediate region.
This characteristic of non-volatility means that CPLDs are often used in modern digital design to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.
CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs (first shipped by Signetics), and PALs.
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kavgoxin
Joined: 17 Sep 2004
Posts: 34
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04 Aug 2006 10:52 diference between fpga and cpld |
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I think the above one is good.
there are few more web resources if you want to see
fpga & cpld
h**p://www.vlsibank.com/sessionspage.asp?titl_id=3057
h**p://www.fpgacpu.org/usenet/synth_cpu.html
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04 Aug 2006 10:52 Ads |
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saubhik
Joined: 27 Apr 2007
Posts: 141
Helped: 8
Location: India
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08 Jun 2007 9:38 Re: Difference Between FPGA & CPLD |
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| bauer wrote: |
A field programmable gate array (FPGA) is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinational functions such as decoders or simple math functions. In most FPGAs, these programmable logic components (or logic blocks, in FPGA parlance) also include memory elements, which may be simple flip-flops or more complete blocks of memories.
A hierarchy of programmable interconnects allows the logic blocks of an FPGA to be interconnected as needed by the system designer, somewhat like a one-chip programmable breadboard. These logic blocks and interconnects can be programmed after the manufacturing process by the customer/designer (hence the term "field programmable") so that the FPGA can perform whatever logical function is needed.
FPGAs are generally slower than their application-specific integrated circuit (ASIC) counterparts, can't handle as complex a design, and draw more power. However, they have several advantages such as a shorter time to market, ability to re-program in the field to fix bugs, and lower non-recurring engineering costs. Vendors can sell cheaper, less flexible versions of their FPGAs which cannot be modified after the design is committed. The development of these designs is made on regular FPGAs and then migrated into a fixed version that more resembles an ASIC. Complex programmable logic devices, or CPLDs, are another alternative.
CPLD stands for Complex Programmable Logic Device. It is a programmable logic device with complexity between that of FPGAs and PALs, and architectural features from both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations.
Features in common with PALs:
* Non-volatile configuration memory. Unlike many FPGAs, an external configuration PROM isn't required, and the CPLD can function immediately on system start-up.
* For all but the largest devices, routing constrains most logic blocks to have input and output signals connected to external pins (little opportunity for internal state storage or deeply layered logic).
Features in common with FPGAs:
* Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.
* Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly-used functions (such as integer arithmetic).
The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD. The differences in architectural approach become more apparent farther from this intermediate region.
This characteristic of non-volatility means that CPLDs are often used in modern digital design to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.
CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs (first shipped by Signetics), and PALs.
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and here is some addition ....
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