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siva_7517
Joined: 16 Jan 2006
Posts: 136
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 31 Jul 2006 11:23 drc error for semi-custom design |
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hi,
I am doing a asic semi-custom design. While doing a drc check in virtuoso, i put a exclude layer on the standard cell to avoid the tools to check the standard cell. This means im only checking the drc for interconnection between the standard cell. Eventually, i still have a errors after doing the drc check. The error is which is violated the rules are :
Via1 size = 0.26 * 0.26
Minimum MetalTop line width = 0.44um
All contacts must be covered with metal1
minimum poly overlap of contact > 0.10
minimum island overlap of contact > 0.10
Can anyone guide me on how to overcome this problem?
And another thing is, can anyone give the proper step to do a drc check.
Thanks in advance
siva
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research235
Joined: 15 Mar 2006
Posts: 274
Helped: 16
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| 31 Jul 2006 11:44 Re: drc error for semi-custom design |
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hello Shiva
could u please tell which DRC checks u are following i mean r using any other tool for DRC , if u r using mentors calibre . i can definately help u .there should not be much prob even if ur using Diva r Dracula rule files . so in any case let us know the procedure
suresh
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siva_7517
Joined: 16 Jan 2006
Posts: 136
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| 31 Jul 2006 11:51 Re: drc error for semi-custom design |
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Hi,
Sorry for the incomplete information.
Well, i am using Diva, Cadence to do the DRC check.
Siva
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research235
Joined: 15 Mar 2006
Posts: 274
Helped: 16
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| 31 Jul 2006 12:17 Re: drc error for semi-custom design |
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hello Shiva,
Since you are using Diva rules file, there are actually not many options to check according to our needs. But there is one way to do so, you can go to the rules file and comment the rules which check VIA and others and then perform DRC, now the tool will ignore all the vias .
I hope it works and this is all u wanted ,
suresh
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shankarmit
Joined: 22 Jun 2005
Posts: 187
Helped: 8
Location: India
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| 31 Jul 2006 18:39 Re: drc error for semi-custom design |
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Hi siva,
You can maually edit the routing.. for example for minimum spacing extend the metal were it show error ensure that it does not metal spacing...
similry for via ... this is via size specified in runset ... create via in smae size ....
Regards
Shankar
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