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sophiefans
Joined: 12 Jun 2006
Posts: 48
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 27 Jul 2006 14:26 Confusion! Keyword:Layout/Virtuoso/LVS |
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I drew a schematic&layout according to a bandgap circuit. When LVS,the BJT number mismatched.
Because the BJT which the parameter "multiplier" was setted "8 " in schematic was recognized as "1" BJT in the netlist,while the "8" BJTs in layout was recongnized as "8".
How could i deal with it?
need your help
3X
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aomeen
Joined: 08 Dec 2005
Posts: 112
Helped: 18
Location: Egypt
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| 27 Jul 2006 14:41 Re: Confusion! Keyword:Layout/Virtuoso/LVS |
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| If the multiplyer of the model is not operating, the only solution is to connect 8 transistors in parallel, each with multiplier equal to 1...
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DenisMark
Joined: 16 Sep 2005
Posts: 314
Helped: 64
Location: Russia
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| 27 Jul 2006 15:17 Re: Confusion! Keyword:Layout/Virtuoso/LVS |
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| LVS rules must have rule for sum parallel instance in one. In this case LVS wil not get u mistake. And Netlists for schematic and layout (how u describe) is right.
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jcpu
Joined: 17 Dec 2005
Posts: 210
Helped: 12
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| 28 Jul 2006 11:08 Re: Confusion! Keyword:Layout/Virtuoso/LVS |
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Dear sophiefans:
When mutiple parallel BJT are connected together,
they often get reduced to one big BJT.
It is really the "total Emitter Area" (AE) that LVS software checked,
but command files have to properly initiate this AE checking function.
Have fun,
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sunny0421
Joined: 30 Mar 2006
Posts: 5
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| 17 Oct 2006 10:58 Confusion! Keyword:Layout/Virtuoso/LVS |
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i think the case is just like thansistors(parallel connection),lvs file only check the total size,you should make 8 bjt as a big one in layout side,but i 'm not quite sure 
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YESH_23
Joined: 20 Dec 2005
Posts: 78
Helped: 4
Location: INDIA
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| 17 Oct 2006 13:49 Confusion! Keyword:Layout/Virtuoso/LVS |
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| the lvs rule dec was unable to reduce the parally commected bjt's just modify that..
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