| Author |
Message |
steven852
Joined: 24 Apr 2005
Posts: 105
Helped: 1
|
 26 Jul 2006 22:24 Positive FF implementation of divided by 5 |
|
|
|
|
Is there an efficient way to implement a divided by 5 circuit with only positive edge FFs?
Thanks.
|
|
| Back to top |
|
 |
bansalr
Joined: 22 Dec 2005
Posts: 155
Helped: 13
|
| 27 Jul 2006 2:38 Re: Positive FF implementation of divided by 5 |
|
|
|
|
If 50% of duty cycle is not required then u can do it very easily with the help of counter.
If 50% duty cycle is required then the output shall be anded with clock to get the required edge.
Added after 3 minutes:
If 50% of duty cycle is not required then u can do it very easily with the help of counter.
If 50% duty cycle is required then the output shall be anded with clock to get the required edge.
|
|
| Back to top |
|
|
nand_gates
Joined: 19 Jul 2004
Posts: 898
Helped: 117
|
| 27 Jul 2006 4:53 Re: Positive FF implementation of divided by 5 |
|
|
|
|
This is the only way I can think of!!
| Code: |
module div5(
// Outputs
clk_out,
// Inputs
clk, reset
);
input clk;
input reset;
output clk_out;
reg [2:0] cnt;
reg cnt_1_r;
assign clk_out = cnt[2];
always @(posedge clk or negedge reset) begin
if (!reset) begin
cnt <= 0;
end else begin
if (cnt == 5)
cnt <= 0;
else
cnt <= cnt + 1;
end
end
endmodule |
|
|
| Back to top |
|
|
steven852
Joined: 24 Apr 2005
Posts: 105
Helped: 1
|
| 27 Jul 2006 5:22 Re: Positive FF implementation of divided by 5 |
|
|
|
|
| Thanks for the code. But I don't think it is a 50% duty cycle divider though.
|
|
| Back to top |
|
|
no_mad
Joined: 10 Dec 2004
Posts: 243
Helped: 19
Location: Naboo
|
| 27 Jul 2006 5:52 Re: Positive FF implementation of divided by 5 |
|
|
|
|
Hi all,
I'm just curious here.
I would like to know why we need a 50% clock cycle in a design. Especially for odd clock divider. (System Level)
Example,
What is the significant difference between 50% cc and 60-40% cc?
(Physical Level -- CTS, synthesis point of view)
Please share some of ur experience.
Thanx in advance
|
|
| Back to top |
|
|
bansalr
Joined: 22 Dec 2005
Posts: 155
Helped: 13
|
| 27 Jul 2006 8:21 Re: Positive FF implementation of divided by 5 |
|
|
|
|
The only problem if u don't have 50% duty cycle when timing is evaluated between negative edge and positive of the same clock. because the margin will be less in one of the case when duty cycle is not 50%.
others plz share.
|
|
| Back to top |
|
|
nand_gates
Joined: 19 Jul 2004
Posts: 898
Helped: 117
|
| 27 Jul 2006 12:02 Re: Positive FF implementation of divided by 5 |
|
|
|
|
In case of DDR I/O one needs clk with 50% duty cycle!!!
example is RLDRAM interface!
|
|
| Back to top |
|
|
dcreddy1980
Joined: 03 Dec 2004
Posts: 129
Helped: 8
Location: Munich, Germany
|
| 27 Jul 2006 16:38 Re: Positive FF implementation of divided by 5 |
|
|
|
|
Hi,
If the design is a FF based...whats the point in having a 60% or 50% duty cycle....u dont see a problem with the STA...if its a latch based...then u need to consider duty cycle...
guys correct me if i am wron !!!
Regards,
dcreddy
|
|
| Back to top |
|
|
steven852
Joined: 24 Apr 2005
Posts: 105
Helped: 1
|
| 28 Jul 2006 5:28 Re: Positive FF implementation of divided by 5 |
|
|
|
|
First of all, it is doable to do a divided by 5 duty cycle by a truth table where the input clk is one of the inputs. But I thought there ought to be more efficient way that this. So I raised my hand. Now it seems optimization the logic function is the best way.
Regarding to the need of 50% duty cycle clock, what you guys mentioned is correct but I would like to add one more thing: it is better for noise harmonics. Remember that if the pulse width changes, the harmonics changes too. When differet pulse widthes exist, the harmonics will modulate eath other. So that is not a good idea to have non-50% duty cycle clock in certain applications.
Just my two cents.
|
|
| Back to top |
|
|
