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hustyw
Joined: 11 Jun 2006
Posts: 14
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 26 Jul 2006 1:59 Compare latch based and register based design |
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| What differences they have? What factors determine certain kind of design?Such as area ,speed ,power, and so on. What else?
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tronix
Joined: 06 Jul 2006
Posts: 121
Helped: 6
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| 26 Jul 2006 19:52 Re: Compare latch based and register based design |
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In terms of speed latch design will always be faster and in general will be using fewer components so lesser area , register design on the other hand will be more robust,stable and less sensitive to noise.
There's a similar thread 'Moore vs Mealy design' in the same forum having similar discussion.
Regards
tronix
Last edited by tronix on 24 Feb 2007 10:37; edited 1 time in total |
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aniketd
Joined: 17 May 2006
Posts: 18
Helped: 3
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| 26 Jul 2006 21:49 Re: Compare latch based and register based design |
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| tags: latch based design |
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to tronix:
There's a similar thread 'Moore vs Mealy design' in the same forum hvn similar discussion
I don't think there is any co-relation between latch based design and register based design with STATE MACHINES what kind of similarity they have?????
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tronix
Joined: 06 Jul 2006
Posts: 121
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| 27 Jul 2006 8:26 Re: Compare latch based and register based design |
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| tags: latch based design advantages of latch vs register |
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| aniketd wrote: |
to tronix:
There's a similar thread 'Moore vs Mealy design' in the same forum hvn similar discussion
I don't think there is any co-relation between latch based design and register based design with STATE MACHINES what kind of similarity they have????? |
Ya sure both r State machines but the similarity is that a Moore Design is a complete synchronous Design possessing advantages and disadvantages of a synchronous Design(immunity to noise,slower speed) , A mealy design on the other hand though synchronous has the attributes of asynchronous design.
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joe2moon
Joined: 19 Apr 2002
Posts: 376
Helped: 12
Location: MOON
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| 28 Jul 2006 6:56 Pulse-latch approach reduces dynamic power |
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| tags: pulsed latch power designs using latch |
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http://www.eetimes.com/news/design/showArticle.jhtml?articleID=190400564
EE Times (07/17/2006 8:00)
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Using pulsed latch instead of flip-flop reduces the dynamic power of the clock network, which can consume half of a chip's dynamic power. Real designs have shown approximately a 20 percent reduction in dynamic power using this methodology.
Pulsed latch concept
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A latch can capture data during the sensitive time determined by the width of clock waveform. If the pulse clock waveform triggers a latch, the latch is synchronized with the clock similarly to edge-triggered flip-flop because the rising and falling edges of the pulse clock are almost identical in terms of timing.
The pulsed latch requires pulse generators that generate pulse clock waveforms with a source clock.
Designing with pulsed latches
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- Pulsed latch replacement and pulse generator insertion
- Skew and slew control of the clock tree
- Timing analysis and optimization
- Power analysis
- Pulse latch design rule checking
Power analysis
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Power analysis must distinguish the pulsed latches and normal flip flops and apply power values appropriately. Moreover, there is additional power consumed in pulse generators and delay cells. These power numbers must be considered during power analysis for comprehensive power savings.
References
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[1] P. Zuchowski, "Design Strategies for Low Power ASICs," IBM Technology Group New England Design Forum, June 18, 2003
[2] Tetsuya Yamada, et.al, "Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core", IEICE Transactions on Electronics 2006 E89-C(3), Pp 287-294
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elec_student
Joined: 21 Nov 2005
Posts: 53
Helped: 4
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| 28 Jul 2006 9:59 Re: Compare latch based and register based design |
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| tags: latch based design |
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| Well latch based designs are not synthesizable. They have race arounf problems thats why we prefer register based designs but naturally latch based designs are more speedy and occupy less area.
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