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leedsuni
Joined: 24 Jul 2006
Posts: 1
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 24 Jul 2006 14:41 interstage matching |
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i am working on the interstage matching of two stagw amplifiers design, but i cant get any useful results, my main aim is to obtain the gain flatness, ineed help !!!!
this is my disign
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MK28
Joined: 07 Mar 2005
Posts: 86
Helped: 3
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| 31 Jul 2006 14:05 Re: interstage matching |
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| is it an IC design or discrete level design? actually to have a gain flatness, you have to have a mismatch between source to load...its called selectively mistmatch..by doing so you get stable gain in all frequencies....
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tomhive
Joined: 26 May 2006
Posts: 31
Helped: 1
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| 19 Dec 2006 15:57 Re: interstage matching |
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| MK28 wrote: |
| is it an IC design or discrete level design? actually to have a gain flatness, you have to have a mismatch between source to load...its called selectively mistmatch..by doing so you get stable gain in all frequencies.... |
hi,
how we can have interstage match, is there any method to get the interstage match, or simply by puting L or C in the interstage.(i am talking abt IC)
thanks
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jaya000
Joined: 02 Jan 2007
Posts: 139
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| 18 Feb 2007 18:04 Re: interstage matching |
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| why not giving real problem along with actual IC no. so that someone can help u?
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