lambtron
Joined: 02 Nov 2005
Posts: 256
Helped: 26
Location: Portland, OR
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 18 Jul 2006 16:17 CSR (Control & Status Registers) Architecture ? |
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The CSR Architecture (specified by ISO/IEC 13213) includes two core registers called STATE_CLEAR and STATE_SET.
The write behavior of these registers is well defined. When you write a value to STATE_CLEAR, all logic-one bits cause the corresponding State Register bits to be cleared. Similarly, when you write to STATE_SET, all logic-one bits cause the corresponding State Register bits to be set.
But what happens when you read these two registers? Is the State Register value only returned through STATE_CLEAR, or can it also be read through STATE_SET? If not, what value should I expect when reading from STATE_SET?
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