mobile communication project on matlab

Goto page 1, 2, 3 Next

EDAboard.com Forum Index -> Digital communication -> mobile communication project on matlab

Author

Message

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

14 Jul 2006 11:11 cdma project

hi every1 i've just finished CDMA project on FPGA boards the design is from A-to-Z DIGITAL even the summation process if any1 interested i can give a hand...,

Last edited by han00oo on 16 Jul 2006 10:50; edited 1 time in total

Google
AdSense
Google Adsense

14 Jul 2006 11:11 Ads

Sorry, but you need login in to view this attachment

rectifier

Joined: 04 Jun 2005
Posts: 117
Helped: 1

14 Jul 2006 11:57 cdma circuits+fpga

We are glad to know the completion of your project on CDMA. I have just submitted the proposal on the same topic so could you please give us the advice for proceeding the project and some details of yours.
thanks ..

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

14 Jul 2006 13:48 cdma handset block diagram

Quote:

could you please give us the advice for proceeding the project

first of all u have to learn about CDMA if u don't have a background yet u can start with the following book "technical introduction to CDMA" u can find it on
www.edaboard.com/viewtopic.php?p=651960#651960

the other main part is FPGA board & how to program it ... i recommend VHDL to do so;

after u r familier with these two parts u can go ahead in the design

& i would be glad to answer any questions regarding the project -isa-

magnetra

Joined: 21 Apr 2005
Posts: 275
Helped: 3
Location: 27.45N, 85.20E KTM, NP

14 Jul 2006 16:39 example design for implimenting cdma in fpga

han00oo, I saw the block diagram of your system. Could you please send the diagram interms of logic gates?
You said "even summation in DIGITAL", did you use XOR gate or OR gate for that purpose?

regards
M

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

14 Jul 2006 19:41 project on fpga

Quote:

You said "even summation in DIGITAL", did you use XOR gate or OR gate for that purpose?

ok..here what i did : i converted digital signal to physical signal & then summation process held & again i returned the summation to Binary before transmission...
did any1 use this technique ???

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

15 Jul 2006 12:52 www.edaboard.com/viewtopic.php?p=651960#651960

hi for any1 wanna learn about CDMA here's agood PDF book to start it's the most interesting book i've ever found regarding CDMA you can download from this link

h**p://www.edaboard.com/viewtopic.php?p=651960#651960

"How CDMA works":

Basic CDMA Principles
• Coding
• Forward and Reverse Channels
CDMA Operational Details
• Multiplexing, Forward and Reverse Power Control
CDMA Handset Architecture
CDMA Handoffs
CDMA Network Architecture
CDMA Messaging and Call Flow
Optional Topics
Wireless Multiple Access Technologies
Overview of Current Technologies
• Capacity; CDMA Overlays, Spectrum Clearing

magnetra

Joined: 21 Apr 2005
Posts: 275
Helped: 3
Location: 27.45N, 85.20E KTM, NP

15 Jul 2006 17:05 cdma fpga

han00oo, can u send me any documents regarding your just completed project? I too am pursuing a similar project.
Thanks
M

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

16 Jul 2006 11:02 spectrum analyzer project fpga

here am gonna start posting more details about my project for any1 interested in CDMA

Part 1 : introduction to :Spread spectrum,FPGA spartan-3 & VHDL

& i'll continue next parts in next posts -isa-

Last edited by han00oo on 03 Nov 2006 19:29; edited 1 time in total

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

17 Jul 2006 9:57 project models related to cdma

Part 2 Tx

Last edited by han00oo on 03 Nov 2006 19:29; edited 1 time in total

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

18 Jul 2006 8:44 cdma project architecture

for more information about the summation process please visit
http://www.edaboard.com/ftopic180923.html

magnetra

Joined: 21 Apr 2005
Posts: 275
Helped: 3
Location: 27.45N, 85.20E KTM, NP

22 Jul 2006 18:32 cdma projects 2009

HanOOoo, the materials posted by you have been extremely helpful to me, please post the remaining materials as well!

Regards
M

rectifier

Joined: 04 Jun 2005
Posts: 117
Helped: 1

22 Jul 2006 18:42 make ur fpga

HanOOoo, could you please give the detail of how the link was made between the transmitter and the receiver?

Regards,
rectifier.

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

23 Jul 2006 13:18 cdma sur fpga

Quote:

could you please give the detail of how the link was made between the transmitter and the receiver?

well , first we wanted the channel to be wireless but we run out of time so we replaced it with wired channel

magnetra

Joined: 21 Apr 2005
Posts: 275
Helped: 3
Location: 27.45N, 85.20E KTM, NP

23 Jul 2006 16:45 project report on cdma

hanOOoo, did you check the spread spectrum using spectrum analyser?? If you did could you post the pics or any data regarding that.

Regards
M

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

23 Jul 2006 21:50 fpga & cdma technique

each block in the uploaded files followed by simulation for it, but this is from Modelsim in FPGApro tool not using spectrum analyser

rectifier

Joined: 04 Jun 2005
Posts: 117
Helped: 1

24 Jul 2006 9:16 current cdma project

Could you please post the remaining part of your project?

thanks ,
rectifier

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

24 Jul 2006 10:27 matlab7.1 project

here's the final part i hope this would help you & if any1 needs more details just ask
Regards,

Hany Hamed

Rx

Last edited by han00oo on 03 Nov 2006 19:30; edited 1 time in total

magnetra

Joined: 21 Apr 2005
Posts: 275
Helped: 3
Location: 27.45N, 85.20E KTM, NP

10 Aug 2006 17:26 project report on fpga

hanOOoo, did you face any "synchronization" problems during your project. For instance, alignment of data bit with PN code width?

M

magnetra

Joined: 21 Apr 2005
Posts: 275
Helped: 3
Location: 27.45N, 85.20E KTM, NP

21 Aug 2006 16:47 project on cdma reports for final year be

hanOOoo, I need some help on implementing the "Integration" unit in VHDL. Could u give me some hints.

M

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

21 Aug 2006 21:00 project about cdma

magnetra wrote:

hanOOoo, I need some help on implementing the "Integration" unit in VHDL. Could u give me some hints.

M

SURE....just tell me what u want

magnetra

Joined: 21 Apr 2005
Posts: 275
Helped: 3
Location: 27.45N, 85.20E KTM, NP

22 Aug 2006 17:43 wcdma fpga projects

how did you perform the integration operation using VHDL?

M

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

23 Aug 2006 19:45 cdma project on fpga

as stated in the uploaded files the Integration part is held on Physical Bits i.e (-1,+1) & after, there's a decision unit which compares the result to reference value;deciding whether it's 1 or 0 user data bit
is that what u mean ??

Hany Hamed

eng.midofidodido

Joined: 20 Jul 2006
Posts: 19
Helped: 1

23 Aug 2006 22:36 block diagram of cdma network

Salam han00oo,

I just wanted to know some information

have you implemented both forward and reverse channel or a single channel only?

Have you implemented a multiple user system or u just maid it as a single user?

How many Spartan 3 Kits did it take u to do it?

regards,

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

24 Aug 2006 13:22 cdma model

hi
as shown in figure in start of postings you can see that data coming from 3 different sources & combined in the transmitter unit then passed to receiver via Real channel (not a modeled in FPGA) thus taking 2 Spartan-3 Kits.

salam,

Hany Hamed

magnetra

Joined: 21 Apr 2005
Posts: 275
Helped: 3
Location: 27.45N, 85.20E KTM, NP

30 Aug 2006 18:35 fpga spartan3 projects

Quote:

the Integration part is held on Physical Bits i.e (-1,+1)

What do u mean by "physical bits"?

M

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

01 Sep 2006 16:42 cdma fpga vhdl

In order for the multiplication principles of CDMA to hold true, bipolar coding is used with the assumed physical values of + 1 and -1. with bipolar coding, logical "1" bits are represented by positive "+1" physical signals, and logical "0" bits are represented by negative " -1" physical signals,and this is also true for Integration part .

Sorry, but you need login in to view this attachment

magnetra

Joined: 21 Apr 2005
Posts: 275
Helped: 3
Location: 27.45N, 85.20E KTM, NP

01 Sep 2006 17:15 cdma-project report

I understand that CDMA principle requires analog integration at the receiver end. How did u perform the integration operation in FPGA?

M

rectifier

Joined: 04 Jun 2005
Posts: 117
Helped: 1

01 Sep 2006 18:57 cdma project making details

dear hanOOoo, could you please tell how you implemented adder in FPGA?

han00oo

Joined: 14 Apr 2006
Posts: 65
Helped: 2
Location: Egypt,Cairo

04 Sep 2006 15:23 cdma in fpga

as i mentioned before the main idea of this project is to change the regular Analog adder with Digital one,& thus the technique I've used is Little bit different from other CDMA types mainly in the adder & integration & here's how it works.

first convert the binary signal to physical signal ,add the physical signals-bitwise- the result would be a multilevel digital signal(number of levels=number of signals+1) -or- for simpilicity we can consider it a regular decimal sequance
the next step is encoding,i encoded the result multilevel signal to a normal digital signal(0.1)
ofcourse the encoded signal has a larger BW but it can be used instead of normal analog adder implemented in digital Design.

Sorry, but you need login in to view this attachment

ravurig

Joined: 21 Jun 2004
Posts: 24
Helped: 1

04 Sep 2006 16:00 fpga project reports

hi ,
hw did u model channel model.
Is it Ricean or Raleigh .......
I didn't see any packet or frame detection.
Nor a Equalizer ,nor a Synchornisation circuits like
coarse synchronisation(or symbol boundary detection),
coarse frequency offset detection,
fine time and frequency synchronisation,
there is no channel estimation also.

bye,
Gopi.

[size=9][color=#999999]Added after 35 seconds:[/color][/size]

hi ,
hw did u model channel model.
Is it Ricean or Raleigh .......
I didn't see any packet or frame detection.
Nor a Equalizer ,nor a Synchornisation circuits like
coarse synchronisation(or symbol boundary detection),
coarse frequency offset detection,
fine time and frequency synchronisation,
there is no channel estimation also.

bye