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ed271828
Joined: 27 Jun 2006
Posts: 16
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 27 Jun 2006 16:32 SystemVerilog synthesizable subset - current vendor support? |
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Hi,
I was wondering if anyone could provide some additional insight on the various tools that support the synthesis of RTL SystemVerilog code. I realize the language has not been standardized yet and that different vendors support different constructs, but I am looking to see if there is a "clear winner" at this point.
Has anyone had the opportunity to work with these tools? I've personally tried Mentor's Precision RTL and @ltera's qu(at)rtus II 6.0. I found Mentor's tool to be a tad buggy and @ltera's.. well.. there's not much support there (yet?)
Thanks,
Ed
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joe2moon
Joined: 19 Apr 2002
Posts: 376
Helped: 12
Location: MOON
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| 29 Jun 2006 13:16 Re: SystemVerilog synthesizable subset - current vendor supp |
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1) SystemVerilog is already the IEEE standard. (IEEE 1800-2005)
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2) FPGA synthesis tool supports SystemVerilog,
- 2.1) Mentor's "Precision RTL Synthesis"
http://www.mentor.com/products/fpga_pld/synthesis/precision_rtl/
- 2.2) Synplicity: Products: Synplify Pro 8.6
http://www.synplicity.com/literature/pdf/synplify86_rnotes.pdf
The synthesis tools support System Verilog enumerated types in accordance with SV LRM section: 4.10. The following subsections are not currently implemented but will be supported in a future release: 4.10.1, 4.10.4.1, 4.10.4.2, 4.10.4.3, 4.10.4.4, 4.10.4.5, 4.10.4.5, 4.10.4.6, 4.10.4.7 .
- 2.3) Synopsys' DC-FPGA
-- http://www.synopsys.com/products/dcfpga/dcfpga_faqs.html
-- http://www.deepchip.com/items/else06-15.html
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ed271828
Joined: 27 Jun 2006
Posts: 16
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| 29 Jun 2006 15:34 Re: SystemVerilog synthesizable subset - current vendor supp |
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The synthesizable subset of SystemVerilog is NOT an IEEE standard.
I looked through solvnet yesterday regarding DC FPGA, and have another question. Does it's support for SystemVerilog relie on (V)HDL Compiler and not DC FPGA directly. If so, it seems that HDL Compiler 2006.06 has "official" (non-beta) support for the language, while 2005.XX (the current release of DC-FPGA) does not. I'm confused in that respect. Either case, I do not believe I have access to a DC-FPGA license. I will have to check.
Mentor's tool is not very mature imho, and Synplicity's support seems very weak.
| joe2moon wrote: |
1) SystemVerilog is already the IEEE standard. (IEEE 1800-2005)
----------------------------------------------------------------------------------
2) FPGA synthesis tool supports SystemVerilog,
- 2.1) Mentor's "Precision RTL Synthesis"
h**p://www.mentor.com/products/fpga_pld/synthesis/precision_rtl/
- 2.2) Synplicity: Products: Synplify Pro 8.6
h**p://www.synplicity.com/literature/pdf/synplify86_rnotes.pdf
The synthesis tools support System Verilog enumerated types in accordance with SV LRM section: 4.10. The following subsections are not currently implemented but will be supported in a future release: 4.10.1, 4.10.4.1, 4.10.4.2, 4.10.4.3, 4.10.4.4, 4.10.4.5, 4.10.4.5, 4.10.4.6, 4.10.4.7 .
- 2.3) Synopsys' DC-FPGA
-- h**p://www.synopsys.com/products/dcfpga/dcfpga_faqs.html
-- h**p://www.deepchip.com/items/else06-15.html |
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