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steven852
Joined: 24 Apr 2005
Posts: 105
Helped: 1
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 27 Jun 2006 1:47 Specific SoC Encounter Flow |
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So far I have prepared the following files for SoC Encounter:
a LEF file, a netlist file, and a SDC file.
According to the manual (search "SoC Encounter Tutorial" on this forum), I am ready to go with Virtual floor plan. However, I am not sure the detail since the tutorial just outlines the steps. Can someone give me some more detail description or documentation that maps the tutorial?
Thanks in advance.
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sree205
Joined: 13 Mar 2006
Posts: 418
Helped: 30
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| 28 Jun 2006 9:51 Specific SoC Encounter Flow |
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| u'll also need a .tlf or a .lib file.
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zhustudio
Joined: 15 Jul 2002
Posts: 104
Helped: 6
Location: China
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| 29 Jun 2006 5:40 Specific SoC Encounter Flow |
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SVP design: .v .lib .sdc .lef (io file, toggle file, cts spec)
Power analysis: voltagestorm library file
Extraction: Same lib with voltagestorm
SI: .cdB file (celtic)
GDS: layer map file.
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amara
Joined: 06 Apr 2006
Posts: 34
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| 29 Jun 2006 7:24 Re: Specific SoC Encounter Flow |
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U need the follwing input files for soc
.v(verilog netlist)
. lef, .lib, .sdc, .cap(capcitance tabfile), io file
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