| Author |
Message |
Thomson
Joined: 15 Oct 2004 Posts: 182 Helped: 3
|
26 Jun 2006 2:37 Aout the percentage of the leakage power consumption! |
|
|
|
|
Hi,
In order to take approapriate measures to analyze the chip-level power dissipation, suitable data sheet for the percentage of the resptive power consumption for the dynaimic, static, leakage portions of the chip shall be know in advance. Although some papers basiclly illustrate the diagram of these proprotions for different CMOS processes; however the data is very obscure.
I'm currently designing the system using CMOS 0.18 3.3v process to realize the ultimate SoC (in fact, different power supply domains exist, here just for simplicity).
Can anybody shares me with the data? Thanks a lot!
Thomson
|
|
| Back to top |
|
 |
nav_vlsi
Joined: 17 Aug 2005 Posts: 48 Helped: 5
|
26 Jun 2006 8:09 Re: Aout the percentage of the leakage power consumption! |
|
|
|
|
| i cant get your question or problem ? could u be more specific ?
|
|
| Back to top |
|
 |
Thomson
Joined: 15 Oct 2004 Posts: 182 Helped: 3
|
26 Jun 2006 8:47 Re: Aout the percentage of the leakage power consumption! |
|
|
|
|
| nav_vlsi wrote: |
| i cant get your question or problem ? could u be more specific ? |
Okay!
Several different CMOS logics are listed as below:
<1> SSRAM: the dynamic and static and leakage power consumpation percentage for all-size and various voltages. I'd like to know the following most:
- SSRAM 0.18um, 1.8v (normal operating condition)
<> size: 512bytes/ 1kbytes/128bytes for dual-port single-port
<2> ordinaly combinational logics(0.18um I think it's ignorable)
<3> DFFs
<4> I/O Pads
Thanks in advance!
Thomson
|
|
| Back to top |
|
 |
eternal_nan
Joined: 10 Mar 2003 Posts: 158 Helped: 15 Location: eternity
|
27 Jun 2006 2:53 Aout the percentage of the leakage power consumption! |
|
|
|
|
Hi Thomson,
First off, you can basically disregard leakage power in most 0.18um processes as it is usually negligably small (on a large digital chip I did of >100million transistors it accounted for <50mw, total consumption was ~20W under load). That is of course not true in case you are using some kind of specialized 0.18 process with lowered threshold voltage, etc.
Anyhow, it is impossible to give you the data you are asking without knowing the exact specifics of the process (along the lines of: TSMC 0.18 LVOD). The power info you are asking for is available in synthesis/primetime libraries (*.lib files) so if you have those you can look it up.
|
|
| Back to top |
|
 |