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zhanch
Joined: 21 Oct 2003
Posts: 31
Helped: 2
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 25 Jun 2006 22:04 block synthesis |
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just wonder whether synopsys DC can do block synthesis. For example, there are serveral modules are the same. Can we ask DC just to synthesis one module, and others using the same netlist and sdf.
Actually, I know synplify ASIC can do this, not sure whether synopsys can do in the same way.
Many thanks,
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jackson_peng
Joined: 11 Apr 2005
Posts: 141
Helped: 13
Location: Shanghai, China
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| 28 Jun 2006 4:27 block synthesis |
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the netlist can be shared if you try a bottom-up synthesis flow.
as for the SDF, i believe it should be merged into the top design, which means most hierarchy name should be prefixed.
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ami
Joined: 28 Apr 2005
Posts: 62
Helped: 4
Location: VN
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| 28 Jun 2006 8:36 Re: block synthesis |
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Hi,
Sure that you can do this in the synthesis process (using DC)! but remember to "uniquify" at the TOP level.
Rgrds,
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rameshsuthapalli
Joined: 27 Jun 2006
Posts: 163
Helped: 19
Location: bangalore,india
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| 28 Jun 2006 11:14 Re: block synthesis |
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| zhanch wrote: |
just wonder whether synopsys DC can do block synthesis. For example, there are serveral modules are the same. Can we ask DC just to synthesis one module, and others using the same netlist and sdf.
Actually, I know synplify ASIC can do this, not sure whether synopsys can do in the same way.
Many thanks, |
for doing the block level u must do the uniqufication frist .
so that it will duplicate the cells accordingly. and it will also duplicate the sdf file.
so that u will get the uniqufied netlist and sdf file which consist of all cell delays and cells.
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