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bb13142
Joined: 22 Jun 2006
Posts: 4
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 22 Jun 2006 10:25 multibank operation of ddr controller |
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I am designing an ddr controller with multibank operation. bank0 is actived and before bank0 is precharged the other bank( bank1/bank2/bank3) will be actived. the aim is to hide the precharge /tcas/ trcd time and improve the efficiency.
but i have no idea about the design.
I have detect too many collsion on DDR bus .
I hope to get your advices about the design. Thanks.
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sree205
Joined: 13 Mar 2006
Posts: 418
Helped: 30
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| 22 Jun 2006 17:43 multibank operation of ddr controller |
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| i'd suggest that you download the simulation models for the corresponding ddr controller from the manufacturer and try to analyze the kind of operations it should support. this is a good start for how to design the controller. this is what i did.
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bb13142
Joined: 22 Jun 2006
Posts: 4
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| 23 Jun 2006 2:30 Re: multibank operation of ddr controller |
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thanks for the reply!
I have already downloaded the simulation model of micron's ddr .
I have successfully designed the ddr controller based on "only one process".
The work flow is : one closed row is actived
--> column selected
-->write or read data ,
--> precharge the opened row.
-->one another row is actived
--> .......
........
BUT Now I want to improve the efficieny .
I want to open one row , before the row is closed i will open another row.
SO in contoller FSM maybe 4 rows are opened.
HOW to avoid the collision on DDR data/addr/control BUS?
HOW TO design the controller?
I want someone help me.
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bb13142
Joined: 22 Jun 2006
Posts: 4
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| 24 Jun 2006 11:02 Re: multibank operation of ddr controller |
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| for your suggest again
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sree205
Joined: 13 Mar 2006
Posts: 418
Helped: 30
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| 26 Jun 2006 17:20 multibank operation of ddr controller |
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Hi, what you are saying is that, you want control signals of one transaction to be passed on even while another transaction is being processed ? am i right ?
if this is the case, then you might have to pipeline the transactions in your controller. will mean adding stages and buffers to store the transactions.
Hope i've given a lead in the right direction.
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bb13142
Joined: 22 Jun 2006
Posts: 4
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| 28 Jun 2006 2:53 Re: multibank operation of ddr controller |
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Thanks for your reply;
You are right about understanding my requirement.
You suggest me to implement it with pipeline technology.
But I find it is difficuity to avoid the collision on DDR data/controll/addr BUS.
how to realize the pipeline ?
I hope to get your advice in detail, thanks very much.
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sree205
Joined: 13 Mar 2006
Posts: 418
Helped: 30
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| 29 Jun 2006 7:53 multibank operation of ddr controller |
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to implement it in pipeline, the way to do it is, when the address phase is going on with one bank, the data phase should be going on in another bank. this way, the address is sent parallely. i believe we have a address bus and a data bus, if i'm not mistaken.
<=================>
data phase1
----<=====>
-----address phase2
---------------------------------<==========>
---------------------------------data phase 2
a good example of pipelining is given in patterson and hennesy's computer architecture book. they have taken a RISC processor and divided it into 5 stages, so, u have to get innovative and try the same thing. to avoid collision or hazards as they are called in the RISC processor, means are given.
so, they have control and data hazards, u could probably have address and data hazards.
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