electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

how to detect fault location in IC for gate level


Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> how to detect fault location in IC for gate level
Author Message
rakesh_aadhimoolam



Joined: 14 Mar 2006
Posts: 218
Helped: 16


Post14 Jun 2006 13:37   

how to detect fault location in IC for gate level


hello folks,,,my project is on now and i want to know how to detect fault location in IC for gate level...

plz help me find out this

thanks in advance
Back to top
Google
AdSense
Google Adsense




Post14 Jun 2006 13:37   

Ads




Back to top
bubu321



Joined: 19 Feb 2006
Posts: 14
Location: Poland


Post14 Jun 2006 18:58   

Re: how to detect fault location in IC for gate level


hi,
- pls try Universal Scan
- make search for U.
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> how to detect fault location in IC for gate level
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
How to locate out fault location in design (4)
How can i detect earth fault? (4)
How to minimise VCD file size for gate-level sim? (2)
how to do gate level simulation on modelsim? (7)
How to import gate-level netlist into ECS ? (5)
How to move gate level netlist to FPGA verification? (5)
How to synthesis (VHDL) all GATE level digital circuit? (9)
how to solve this $setup violation in gate-level simulation (4)
How to calculate power consumption During the Gate Level Sim (3)
Convert gate level design to transistor level desig (1)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS