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Message |
hover
Joined: 12 Jun 2004
Posts: 23
Location: China
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 06 Jun 2006 6:01 state machine coding styles |
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Hi, below there are two types of state machine coding styles.
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1. always@(posedge clk or negedge rst_n)
...
current_state <= next_state;
...
always@(current_state)
...
case(current_state)
...
s1:
if...
next_state = s2;
...
...
always@(posedge clk or negedge rst_n)
...
else
a <= 1'b0;
b <= 1'b0;
c <= 1'b0;
case(current_state)
s1:
a<=1'b1;
s2:
b<=1'b1;
s3:
c<=1'b1;
default:
....
2. always@(posedge clk or negedge rst_n)
...
current_state <= next_state;
...
always@(current_state)
...
a = 1'b0;
b = 1'b0;
c = 1'b0;
case(current_state)
...
s1:
if...
begin
next_state = s2;
a=1'b1;
end
s2:
if...
begin
next_state = s3
b=1'b1;
end
s3:
c=1'b1;
default:
......... |
It is said that the first one format of the two state machines is a standard and better one. But for the first one, there is one clock period latency with a, b and c signal. For some cases, it will not be good.
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spauls
Joined: 17 Dec 2002
Posts: 547
Helped: 19
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| 06 Jun 2006 12:44 Re: state machine coding styles |
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| Io latency will not be affected much by State machine logic.
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r63511
Joined: 26 Jul 2006
Posts: 27
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| 26 Jul 2006 18:16 state machine coding styles |
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| in the second design, the output might contain a lot of glitches, which is very dangerous if used directly to drive other combinational logic.
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