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kaushiksangam
Joined: 09 Apr 2006
Posts: 14
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 05 Jun 2006 19:14 Question on VHDL |
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| Is there a function to convert an vector datatype to integer and vice versa.
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Ahmed Ragab
Joined: 30 Jun 2004
Posts: 351
Helped: 118
Location: Egypt
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| 05 Jun 2006 22:26 Re: Question on VHDL |
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| tags: vhdl variable unsigned integer vhdl integer std_logic_vector |
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Well I don't think there is a ready made function to convert, but you can write down your own easily.
example:
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-- Convert a std_logic_vector to an unsigned integer
--
function to_uint (a: std_logic_vector) return integer is
alias av: std_logic_vector (1 to a'length) is a;
variable val: integer := 0;
variable b: integer := 1 ;
begin
for i in a'length downto 1 loop
if (av(i) = '1 ') then -- if LSB is '1 ',
val := vat + b; -- add value for current bit position
end if;
b := b*2; -- Shift left 1 bit
end loop;
return val;
end to_uint;
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Example from "VHDL Made Easy" by Pellerin and Taylor.
p.s. if you find this post of any use to you then kindly do click on the "helped me" icon. Regards, salam.
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salma ali bakr
Joined: 27 Jan 2006
Posts: 945
Helped: 79
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| 06 Jun 2006 8:09 Re: Question on VHDL |
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| tags: conv_signed vhdl vhdl integer std_logic_vector vhdl conv_integer conv_unsigned conv_unsigned in vhdl vhdl conv_unsigned conv_unsigned vhdl |
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Std_Logic_Arith
The following functions are contained in the library arith.vhd. To use them,
place the line “USE ieee.std_logic_arith.ALL” at the beginning of your
VHDL design.
FUNCTION Pass(arg, size) Return
· CONV_INTEGER INTEGER INTEGER
· CONV_INTEGER UNSIGNED INTEGER
· CONV_INTEGER SIGNED INTEGER
· CONV_INTEGER STD_ULOGIC SMALL_INT;
· CONV_UNSIGNED INTEGER, INTEGER UNSIGNED;
· CONV_UNSIGNED UNSIGNED, INTEGER UNSIGNED;
· CONV_UNSIGNED SIGNED, INTEGER UNSIGNED;
· CONV_UNSIGNED STD_ULOGIC, INTEGER UNSIGNED;
· CONV_SIGNED INTEGER, INTEGER SIGNED;
· CONV_SIGNED UNSIGNED, INTEGER SIGNED;
· CONV_SIGNED SIGNED, INTEGER SIGNED;
· CONV_SIGNED STD_ULOGIC, INTEGER SIGNED;
· CONV_STD_LOGIC_VECTOR INTEGER, INTEGER STD_LOGIC_VECTOR
· CONV_STD_LOGIC_VECTOR UNSIGNED, INTEGER STD_LOGIC_VECTOR
· CONV_STD_LOGIC_VECTOR SIGNED, INTEGER STD_LOGIC_VECTOR
· CONV_STD_LOGIC_VECTOR STD_ULOGIC, INTEGER STD_LOGIC_VECTOR
· EXT STD_LOGIC_VECTOR, INTEGER STD_LOGIC_VECTOR;
· SXT STD_LOGIC_VECTOR, INTEGER STD_LOGIC_VECTOR;
/////////////////////////////////////////////////////////////////////////////////////////////
Std_Logic_Unsigned
The following function is contained in the library unsigned.vhd. To use it, place
the line “USE ieee.std_logic_unsigned.ALL” at the beginning of your VHDL
design.
· CONV_INTEGER(arg: STD_LOGIC_VECTOR) return INTEGER;
/////////////////////////////////////////////////////////////////////////////////////////////
Std_Logic_Signed
The following function is contained in the library signed.vhd. To use it, place
the line “USE ieee.std_logic_signed.ALL” at the beginning of your VHDL
design.
· CONV_INTEGER(arg: STD_LOGIC_VECTOR) return INTEGER;
/////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////
u can find all info such as the above in this link:
http://www.quicklogic.com/images/quicknote45.pdf
good luck
Salma:D
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omara007
Joined: 06 Jan 2003
Posts: 1172
Helped: 35
Location: Dubai
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| 24 Jun 2008 21:17 Question on VHDL |
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| Unfortunately std_logic_arith is obsolute and should no more be used. Instead, numeric_std should exclusively be used.
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karikalan_t79
Joined: 20 Oct 2008
Posts: 99
Helped: 1
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| 23 Oct 2008 4:48 Re: Question on VHDL |
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| ya, use nuemric_std or synopsys lib is good for this conversions
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