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xilinx fpga router error,can someone heip me?
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shoufeng_luo



Joined: 23 Aug 2005
Posts: 10
Helped: 1
Post29 May 2006 15:16   

xilinx fpga router error,can someone heip me?
Hello everyone, I use a pair of LVDS signals as the differential clks of DCM,When implementing the design ,I encounter an error as follow:This design contains an LVDS pair.The pair of IOs must be palced in a specific relatice structure.What should I do to correct the error?Thanks !
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maksya



Joined: 02 Jun 2005
Posts: 172
Helped: 13
Post29 May 2006 19:09   

xilinx fpga router error,can someone heip me?
Place pins correctly! There must be some guidelines in Xilinx's documentation for your FPGA refered to "PCB Layout" or "Pad Placement & DC Guidelines". For example, Altera's Cyclone have such restrictions:

- Single-ended inputs may be only be placed four or more pads away from a differential pad.
- Single-ended outputs and bidirectional pads may only be placed five or more pads away from a differential pad.
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EDALIST



Joined: 27 Nov 2004
Posts: 133
Helped: 13
Post29 May 2006 20:05   

Re: xilinx fpga router error,can someone heip me?
you are in big problem since they are dedicated pins (you probebly using GC).

the only solution i see is to use the clock as single ended clock signal.
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shoufeng_luo



Joined: 23 Aug 2005
Posts: 10
Helped: 1
Post30 May 2006 5:25   

Re: xilinx fpga router error,can someone heip me?
Thanks a lot,a pair of differential signals should be connected to a pair of differential pads of fpga.But I connect them to two pads not be a pair.So the error happens.I obliged to use a sigle ended colck.
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